//\r
\r
// Write VBAR - The Exception Vector table must be aligned to its requirement\r
- ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
+ //TODO: Fix baseTools to ensure the Exception Vector Table is correctly aligned in AArch64\r
+ //ASSERT(((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r
ArmWriteVBar ((UINTN)PeiVectorTable);\r
\r
//Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r