MdeModulePkg/EhciDxe: enable 64-bit PCI DMA

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / EhciDxe / EhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
index 7a533d78e13d9afd81a025985cdcee6082f78b9d..88a66aee71028ced1cf80bc1eac4d8a20e59c1c9 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
@@ -2,8 +2,8 @@
 \r
   The EHCI register operation routines.\r
 \r
-Copyright (c) 2007 - 2009, Intel Corporation\r
-All rights reserved. This program and the accompanying materials\r
+Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r
+This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
@@ -53,6 +53,42 @@ EhcReadCapRegister (
   return Data;\r
 }\r
 \r
+/**\r
+  Read EHCI debug port register.\r
+\r
+  @param  Ehc          The EHCI device.\r
+  @param  Offset       Debug port register offset.\r
+\r
+  @return The register content read.\r
+  @retval If err, return 0xffff.\r
+\r
+**/\r
+UINT32\r
+EhcReadDbgRegister (\r
+  IN  USB2_HC_DEV         *Ehc,\r
+  IN  UINT32              Offset\r
+  )\r
+{\r
+  UINT32                  Data;\r
+  EFI_STATUS              Status;\r
+\r
+  Status = Ehc->PciIo->Mem.Read (\r
+                             Ehc->PciIo,\r
+                             EfiPciIoWidthUint32,\r
+                             Ehc->DebugPortBarNum,\r
+                             (UINT64) (Ehc->DebugPortOffset + Offset),\r
+                             1,\r
+                             &Data\r
+                             );\r
+\r
+  if (EFI_ERROR (Status)) {\r
+    DEBUG ((EFI_D_ERROR, "EhcReadDbgRegister: Pci Io read error - %r at %d\n", Status, Offset));\r
+    Data = 0xFFFF;\r
+  }\r
+\r
+  return Data;\r
+}\r
+\r
 \r
 /**\r
   Read EHCI Operation register.\r
@@ -554,6 +590,7 @@ EhcInitHC (
   )\r
 {\r
   EFI_STATUS              Status;\r
+  UINT32                  Index;\r
 \r
   // This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.\r
   // This ASSERT needs to be removed so the BeagleBoard will boot. When we fix\r
@@ -564,7 +601,7 @@ EhcInitHC (
   // Allocate the periodic frame and associated memeory\r
   // management facilities if not already done.\r
   //\r
-  if (Ehc->PeriodFrameHost != NULL) {\r
+  if (Ehc->PeriodFrame != NULL) {\r
     EhcFreeSched (Ehc);\r
   }\r
 \r
@@ -573,32 +610,36 @@ EhcInitHC (
   if (EFI_ERROR (Status)) {\r
     return Status;\r
   }\r
-  //\r
-  // 1. Program the CTRLDSSEGMENT register with the high 32 bit addr\r
-  //\r
-  EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);\r
 \r
   //\r
-  // 2. Clear USBINTR to disable all the interrupt. UEFI works by polling\r
+  // 1. Clear USBINTR to disable all the interrupt. UEFI works by polling\r
   //\r
   EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
 \r
   //\r
-  // 3. Program periodic frame list, already done in EhcInitSched\r
-  // 4. Start the Host Controller\r
+  // 2. Start the Host Controller\r
   //\r
   EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
 \r
   //\r
-  // 5. Set all ports routing to EHC\r
+  // 3. Power up all ports if EHCI has Port Power Control (PPC) support\r
   //\r
-  EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+  if (Ehc->HcStructParams & HCSP_PPC) {\r
+    for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {\r
+      EhcSetOpRegBit (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), PORTSC_POWER);\r
+    }\r
+  }\r
 \r
   //\r
   // Wait roothub port power stable\r
   //\r
   gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);\r
 \r
+  //\r
+  // 4. Set all ports routing to EHC\r
+  //\r
+  EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+\r
   Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
 \r
   if (EFI_ERROR (Status)) {\r