MdeModulePkg/IdeBusPei: Fix undefined behavior in signed left shift

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.c

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
index c863f22d250d512c98f85981462f3cf5bec9d9b3..4d5937de538f8b907c44ec5ecf1a002a44ef3cfc 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
@@ -2,7 +2,7 @@
 \r
   The XHCI register operation routines.\r
 \r
-Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -112,7 +112,7 @@ XhcReadOpReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->CapLength + Offset),\r
+                             Xhc->CapLength + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -148,7 +148,7 @@ XhcWriteOpReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->CapLength + Offset),\r
+                             Xhc->CapLength + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -181,7 +181,7 @@ XhcWriteOpReg16 (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint16,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->CapLength + Offset),\r
+                             Xhc->CapLength + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -215,7 +215,7 @@ XhcReadDoorBellReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->DBOff + Offset),\r
+                             Xhc->DBOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -251,7 +251,7 @@ XhcWriteDoorBellReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->DBOff + Offset),\r
+                             Xhc->DBOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -285,7 +285,7 @@ XhcReadRuntimeReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->RTSOff + Offset),\r
+                             Xhc->RTSOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -321,7 +321,7 @@ XhcWriteRuntimeReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->RTSOff + Offset),\r
+                             Xhc->RTSOff + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -355,7 +355,7 @@ XhcReadExtCapReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->ExtCapRegBase + Offset),\r
+                             Xhc->ExtCapRegBase + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -391,7 +391,7 @@ XhcWriteExtCapReg (
                              Xhc->PciIo,\r
                              EfiPciIoWidthUint32,\r
                              XHC_BAR_INDEX,\r
-                             (UINT64) (Xhc->ExtCapRegBase + Offset),\r
+                             Xhc->ExtCapRegBase + Offset,\r
                              1,\r
                              &Data\r
                              );\r
@@ -515,16 +515,16 @@ XhcWaitOpRegBit (
   )\r
 {\r
   UINT32                  Index;\r
-  UINTN                   Loop;\r
+  UINT64                  Loop;\r
 \r
-  Loop   = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;\r
+  Loop   = Timeout * XHC_1_MILLISECOND;\r
 \r
   for (Index = 0; Index < Loop; Index++) {\r
     if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
       return EFI_SUCCESS;\r
     }\r
 \r
-    gBS->Stall (XHC_POLL_DELAY);\r
+    gBS->Stall (XHC_1_MICROSECOND);\r
   }\r
 \r
   return EFI_TIMEOUT;\r
@@ -543,6 +543,10 @@ XhcSetBiosOwnership (
 {\r
   UINT32                    Buffer;\r
 \r
+  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
+    return;\r
+  }\r
+\r
   DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));\r
 \r
   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
@@ -563,6 +567,10 @@ XhcClearBiosOwnership (
 {\r
   UINT32                    Buffer;\r
 \r
+  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
+    return;\r
+  }\r
+\r
   DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));\r
 \r
   Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
@@ -606,7 +614,7 @@ XhcGetCapabilityAddr (
     ExtCapOffset += (NextExtCapReg << 2);\r
   } while (NextExtCapReg != 0);\r
 \r
-  return 0;\r
+  return 0xFFFFFFFF;\r
 }\r
 \r
 /**\r
@@ -676,9 +684,15 @@ XhcResetHC (
     }\r
   }\r
 \r
-  if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
+  if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
       ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {\r
     XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
+    //\r
+    // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.\r
+    // Otherwise there may have the timeout case happened.\r
+    // The below is a workaround to solve such problem.\r
+    //\r
+    gBS->Stall (XHC_1_MILLISECOND);\r
     Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
   }\r
 \r