Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.\r
Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
- This program and the accompanying materials are licensed and made\r
- available under the terms and conditions of the BSD License which\r
- accompanies this distribution. The full text of the license may\r
- be found at http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
-#include <Library/PcdLib.h>\r
#include <OvmfPlatforms.h>\r
\r
-//\r
-// Power Management PCI Configuration Register fields\r
-//\r
-#define PMBA_RTE BIT0\r
-#define PIIX4_PMIOSE BIT0\r
-#define Q35_ACPI_EN BIT7\r
-\r
-//\r
-// Offset in the Power Management Base Address to the ACPI Timer\r
-//\r
-#define ACPI_TIMER_OFFSET 0x8\r
-\r
/**\r
The constructor function enables ACPI IO space.\r
\r
{\r
UINT16 HostBridgeDevId;\r
UINTN Pmba;\r
+ UINT32 PmbaAndVal;\r
+ UINT32 PmbaOrVal;\r
UINTN AcpiCtlReg;\r
UINT8 AcpiEnBit;\r
\r
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (0x80); // PMREGMISC\r
- AcpiEnBit = PIIX4_PMIOSE;\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
+ PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
+ PmbaOrVal = PIIX4_PMBA_VALUE;\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
- AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (0x44); // ACPI_CNTL\r
- AcpiEnBit = Q35_ACPI_EN;\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
+ PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
+ PmbaOrVal = ICH9_PMBASE_VALUE;\r
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
//\r
// If the Power Management Base Address is not programmed,\r
- // then program the Power Management Base Address from a PCD.\r
+ // then program it now.\r
//\r
- PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
+ PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
\r
//\r
// Enable PMBA I/O port decodes\r
HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
switch (HostBridgeDevId) {\r
case INTEL_82441_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
break;\r
case INTEL_Q35_MCH_DEVICE_ID:\r
- Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
break;\r
default:\r
DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r