#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgS3Lib.h>\r
+#include <Library/QemuFwCfgSimpleParserLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
-#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
+#include <IndustryStandard/I440FxPiix4.h>\r
#include <IndustryStandard/Pci22.h>\r
+#include <IndustryStandard/Q35MchIch9.h>\r
+#include <IndustryStandard/QemuCpuHotplug.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
-EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
- { EfiACPIMemoryNVS, 0x004 },\r
- { EfiACPIReclaimMemory, 0x008 },\r
- { EfiReservedMemoryType, 0x004 },\r
- { EfiRuntimeServicesData, 0x024 },\r
- { EfiRuntimeServicesCode, 0x030 },\r
- { EfiBootServicesCode, 0x180 },\r
- { EfiBootServicesData, 0xF00 },\r
- { EfiMaxMemoryType, 0x000 }\r
-};\r
-\r
-\r
EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
{\r
EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
PciIoBase = 0xC000;\r
PciIoSize = 0x4000;\r
\r
- //\r
- // Create Memory Type Information HOB\r
- //\r
- BuildGuidDataHob (\r
- &gEfiMemoryTypeInformationGuid,\r
- mDefaultMemoryTypeInformation,\r
- sizeof(mDefaultMemoryTypeInformation)\r
- );\r
-\r
//\r
// Video memory + Legacy BIOS region\r
//\r
\r
TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
PciExBarBase = 0;\r
- PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;\r
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
//\r
// The MMCONFIG area is expected to fall between the top of low RAM and\r
ASSERT (TopOfLowRam <= PciExBarBase);\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
- PciSize = 0xFC000000 - PciBase;\r
} else {\r
- PciSize = 0xFC000000 - PciBase;\r
+ ASSERT (TopOfLowRam <= mQemuUc32Base);\r
+ PciBase = mQemuUc32Base;\r
}\r
\r
//\r
// 0xFED20000 gap 896 KB\r
// 0xFEE00000 LAPIC 1 MB\r
//\r
+ PciSize = 0xFC000000 - PciBase;\r
AddIoMemoryBaseSizeHob (PciBase, PciSize);\r
PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
}\r
\r
-EFI_STATUS\r
-GetNamedFwCfgBoolean (\r
- IN CHAR8 *FwCfgFileName,\r
- OUT BOOLEAN *Setting\r
- )\r
-{\r
- EFI_STATUS Status;\r
- FIRMWARE_CONFIG_ITEM FwCfgItem;\r
- UINTN FwCfgSize;\r
- UINT8 Value[3];\r
-\r
- Status = QemuFwCfgFindFile (FwCfgFileName, &FwCfgItem, &FwCfgSize);\r
- if (EFI_ERROR (Status)) {\r
- return Status;\r
- }\r
- if (FwCfgSize > sizeof Value) {\r
- return EFI_BAD_BUFFER_SIZE;\r
- }\r
- QemuFwCfgSelectItem (FwCfgItem);\r
- QemuFwCfgReadBytes (FwCfgSize, Value);\r
-\r
- if ((FwCfgSize == 1) ||\r
- (FwCfgSize == 2 && Value[1] == '\n') ||\r
- (FwCfgSize == 3 && Value[1] == '\r' && Value[2] == '\n')) {\r
- switch (Value[0]) {\r
- case '0':\r
- case 'n':\r
- case 'N':\r
- *Setting = FALSE;\r
- return EFI_SUCCESS;\r
-\r
- case '1':\r
- case 'y':\r
- case 'Y':\r
- *Setting = TRUE;\r
- return EFI_SUCCESS;\r
-\r
- default:\r
- break;\r
- }\r
- }\r
- return EFI_PROTOCOL_ERROR;\r
-}\r
-\r
#define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \\r
do { \\r
BOOLEAN Setting; \\r
RETURN_STATUS PcdStatus; \\r
\\r
- if (!EFI_ERROR (GetNamedFwCfgBoolean ( \\r
+ if (!RETURN_ERROR (QemuFwCfgParseBool ( \\r
"opt/ovmf/" #TokenName, &Setting))) { \\r
PcdStatus = PcdSetBoolS (TokenName, Setting); \\r
ASSERT_RETURN_ERROR (PcdStatus); \\r
VOID\r
)\r
{\r
- UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable);\r
UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack);\r
}\r
\r
AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
break;\r
default:\r
- DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
+ DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
__FUNCTION__, mHostBridgeDevId));\r
ASSERT (FALSE);\r
return;\r
AllocateRuntimePages (\r
EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
);\r
- DEBUG ((EFI_D_INFO,\r
+ DEBUG ((DEBUG_INFO,\r
"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
VariableStore,\r
(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
{\r
UINT32 Loop;\r
\r
- DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
+ DEBUG ((DEBUG_INFO, "CMOS:\n"));\r
\r
for (Loop = 0; Loop < 0x80; Loop++) {\r
if ((Loop % 0x10) == 0) {\r
- DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
+ DEBUG ((DEBUG_INFO, "%02x:", Loop));\r
}\r
- DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
+ DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));\r
if ((Loop % 0x10) == 0xf) {\r
- DEBUG ((EFI_D_INFO, "\n"));\r
+ DEBUG ((DEBUG_INFO, "\n"));\r
}\r
}\r
}\r
{\r
#if defined (MDE_CPU_X64)\r
if (FeaturePcdGet (PcdSmmSmramRequire) && mS3Supported) {\r
- DEBUG ((EFI_D_ERROR,\r
+ DEBUG ((DEBUG_ERROR,\r
"%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n", __FUNCTION__));\r
- DEBUG ((EFI_D_ERROR,\r
+ DEBUG ((DEBUG_ERROR,\r
"%a: Please disable S3 on the QEMU command line (see the README),\n",\r
__FUNCTION__));\r
- DEBUG ((EFI_D_ERROR,\r
+ DEBUG ((DEBUG_ERROR,\r
"%a: or build OVMF with \"OvmfPkgIa32X64.dsc\".\n", __FUNCTION__));\r
ASSERT (FALSE);\r
CpuDeadLoop ();\r
}\r
\r
\r
+VOID\r
+Q35BoardVerification (\r
+ VOID\r
+ )\r
+{\r
+ if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+ return;\r
+ }\r
+\r
+ DEBUG ((\r
+ DEBUG_ERROR,\r
+ "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
+ "only DID=0x%04x (Q35) is supported\n",\r
+ __FUNCTION__,\r
+ mHostBridgeDevId,\r
+ INTEL_Q35_MCH_DEVICE_ID\r
+ ));\r
+ ASSERT (FALSE);\r
+ CpuDeadLoop ();\r
+}\r
+\r
+\r
/**\r
- Fetch the number of boot CPUs from QEMU and expose it to UefiCpuPkg modules.\r
- Set the mMaxCpuCount variable.\r
+ Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
+ them to UefiCpuPkg modules. Set the mMaxCpuCount variable.\r
**/\r
VOID\r
MaxCpuCountInitialization (\r
VOID\r
)\r
{\r
- UINT16 ProcessorCount;\r
+ UINT16 BootCpuCount;\r
RETURN_STATUS PcdStatus;\r
\r
- QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
- ProcessorCount = QemuFwCfgRead16 ();\r
//\r
- // If the fw_cfg key or fw_cfg entirely is unavailable, load mMaxCpuCount\r
- // from the PCD default. No change to PCDs.\r
+ // Try to fetch the boot CPU count.\r
//\r
- if (ProcessorCount == 0) {\r
+ QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
+ BootCpuCount = QemuFwCfgRead16 ();\r
+ if (BootCpuCount == 0) {\r
+ //\r
+ // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let\r
+ // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or\r
+ // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached\r
+ // first).\r
+ //\r
+ DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));\r
mMaxCpuCount = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
- return;\r
+ } else {\r
+ //\r
+ // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to\r
+ // (BootCpuCount - 1) precisely, regardless of timeout.\r
+ //\r
+ // Now try to fetch the possible CPU count.\r
+ //\r
+ UINTN CpuHpBase;\r
+ UINT32 CmdData2;\r
+\r
+ CpuHpBase = ((mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r
+ ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);\r
+\r
+ //\r
+ // If only legacy mode is available in the CPU hotplug register block, or\r
+ // the register block is completely missing, then the writes below are\r
+ // no-ops.\r
+ //\r
+ // 1. Switch the hotplug register block to modern mode.\r
+ //\r
+ IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r
+ //\r
+ // 2. Select a valid CPU for deterministic reading of\r
+ // QEMU_CPUHP_R_CMD_DATA2.\r
+ //\r
+ // CPU#0 is always valid; it is the always present and non-removable\r
+ // BSP.\r
+ //\r
+ IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r
+ //\r
+ // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to\r
+ // read as zero, and which does not invalidate the selector. (The\r
+ // selector may change, but it must not become invalid.)\r
+ //\r
+ // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.\r
+ //\r
+ IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);\r
+ //\r
+ // 4. Read QEMU_CPUHP_R_CMD_DATA2.\r
+ //\r
+ // If the register block is entirely missing, then this is an unassigned\r
+ // IO read, returning all-bits-one.\r
+ //\r
+ // If only legacy mode is available, then bit#0 stands for CPU#0 in the\r
+ // "CPU present bitmap". CPU#0 is always present.\r
+ //\r
+ // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning\r
+ // all-bits-zero), or it is specified to read as zero after the above\r
+ // steps. Both cases confirm modern mode.\r
+ //\r
+ CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);\r
+ DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));\r
+ if (CmdData2 != 0) {\r
+ //\r
+ // QEMU doesn't support the modern CPU hotplug interface. Assume that the\r
+ // possible CPU count equals the boot CPU count (precluding hotplug).\r
+ //\r
+ DEBUG ((DEBUG_WARN, "%a: modern CPU hotplug interface unavailable\n",\r
+ __FUNCTION__));\r
+ mMaxCpuCount = BootCpuCount;\r
+ } else {\r
+ //\r
+ // Grab the possible CPU count from the modern CPU hotplug interface.\r
+ //\r
+ UINT32 Present, Possible, Selected;\r
+\r
+ Present = 0;\r
+ Possible = 0;\r
+\r
+ //\r
+ // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures\r
+ // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,\r
+ // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending\r
+ // hotplug events; therefore, select CPU#0 forcibly.\r
+ //\r
+ IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r
+\r
+ do {\r
+ UINT8 CpuStatus;\r
+\r
+ //\r
+ // Read the status of the currently selected CPU. This will help with a\r
+ // sanity check against "BootCpuCount".\r
+ //\r
+ CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);\r
+ if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {\r
+ ++Present;\r
+ }\r
+ //\r
+ // Attempt to select the next CPU.\r
+ //\r
+ ++Possible;\r
+ IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r
+ //\r
+ // If the selection is successful, then the following read will return\r
+ // the selector (which we know is positive at this point). Otherwise,\r
+ // the read will return 0.\r
+ //\r
+ Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);\r
+ ASSERT (Selected == Possible || Selected == 0);\r
+ } while (Selected > 0);\r
+\r
+ //\r
+ // Sanity check: fw_cfg and the modern CPU hotplug interface should\r
+ // return the same boot CPU count.\r
+ //\r
+ if (BootCpuCount != Present) {\r
+ DEBUG ((DEBUG_WARN, "%a: QEMU v2.7 reset bug: BootCpuCount=%d "\r
+ "Present=%u\n", __FUNCTION__, BootCpuCount, Present));\r
+ //\r
+ // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus\r
+ // platform reset (including S3), was corrected in QEMU commit\r
+ // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device added\r
+ // CPUs", 2016-11-16), part of release v2.8.0.\r
+ //\r
+ BootCpuCount = (UINT16)Present;\r
+ }\r
+\r
+ mMaxCpuCount = Possible;\r
+ }\r
}\r
- //\r
- // Otherwise, set mMaxCpuCount to the value reported by QEMU.\r
- //\r
- mMaxCpuCount = ProcessorCount;\r
- //\r
- // Additionally, tell UefiCpuPkg modules (a) the exact number of VCPUs, (b)\r
- // to wait, in the initial AP bringup, exactly as long as it takes for all of\r
- // the APs to report in. For this, we set the longest representable timeout\r
- // (approx. 71 minutes).\r
- //\r
- PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, ProcessorCount);\r
+\r
+ DEBUG ((DEBUG_INFO, "%a: BootCpuCount=%d mMaxCpuCount=%u\n", __FUNCTION__,\r
+ BootCpuCount, mMaxCpuCount));\r
+ ASSERT (BootCpuCount <= mMaxCpuCount);\r
+\r
+ PcdStatus = PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- PcdStatus = PcdSet32S (PcdCpuApInitTimeOutInMicroSeconds, MAX_UINT32);\r
+ PcdStatus = PcdSet32S (PcdCpuMaxLogicalProcessorNumber, mMaxCpuCount);\r
ASSERT_RETURN_ERROR (PcdStatus);\r
- DEBUG ((DEBUG_INFO, "%a: QEMU reports %d processor(s)\n", __FUNCTION__,\r
- ProcessorCount));\r
}\r
\r
\r
XenDetect ();\r
\r
if (QemuFwCfgS3Enabled ()) {\r
- DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
+ DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r
mS3Supported = TRUE;\r
Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
ASSERT_EFI_ERROR (Status);\r
S3Verification ();\r
BootModeInitialization ();\r
AddressWidthInitialization ();\r
- MaxCpuCountInitialization ();\r
\r
//\r
// Query Host Bridge DID\r
//\r
mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
+ MaxCpuCountInitialization ();\r
+\r
if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
+ Q35BoardVerification ();\r
Q35TsegMbytesInitialization ();\r
+ Q35SmramAtDefaultSmbaseInitialization ();\r
}\r
\r
PublishPeiMemory ();\r
\r
+ QemuUc32BaseInitialization ();\r
+\r
InitializeRamRegions ();\r
\r
if (mXen) {\r
- DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
+ DEBUG ((DEBUG_INFO, "Xen was detected\n"));\r
InitializeXen ();\r
}\r
\r
ReserveEmuVariableNvStore ();\r
}\r
PeiFvInitialization ();\r
+ MemTypeInfoInitialization ();\r
MemMapInitialization ();\r
NoexecDxeInitialization ();\r
}\r
projects / mirror_edk2.git / blobdiff