OvmfPkg/PlatformPei: remove mPlatformInfoHob

[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index 4cd77fd5f84fc72334be2a23aca7d1dc6f6795ca..ebce2ba1290e794c2375fb8460bea31e64b484d1 100644 (file)
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -41,8 +41,6 @@
 \r
 #include "Platform.h"\r
 \r
-EFI_HOB_PLATFORM_INFO  mPlatformInfoHob = { 0 };\r
-\r
 EFI_PEI_PPI_DESCRIPTOR  mPpiBootMode[] = {\r
   {\r
     EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
@@ -75,16 +73,17 @@ MemMapInitialization (
   ASSERT_RETURN_ERROR (PcdStatus);\r
 }\r
 \r
+STATIC\r
 VOID\r
 NoexecDxeInitialization (\r
-  VOID\r
+  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
   )\r
 {\r
   RETURN_STATUS  Status;\r
 \r
-  Status = PlatformNoexecDxeInitialization (&mPlatformInfoHob);\r
+  Status = PlatformNoexecDxeInitialization (PlatformInfoHob);\r
   if (!RETURN_ERROR (Status)) {\r
-    Status = PcdSetBoolS (PcdSetNxForStack, mPlatformInfoHob.PcdSetNxForStack);\r
+    Status = PcdSetBoolS (PcdSetNxForStack, PlatformInfoHob->PcdSetNxForStack);\r
     ASSERT_RETURN_ERROR (Status);\r
   }\r
 }\r
@@ -230,13 +229,14 @@ ReserveEmuVariableNvStore (
   ASSERT_RETURN_ERROR (PcdStatus);\r
 }\r
 \r
+STATIC\r
 VOID\r
 S3Verification (\r
-  VOID\r
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
   )\r
 {\r
  #if defined (MDE_CPU_X64)\r
-  if (mPlatformInfoHob.SmmSmramRequire && mPlatformInfoHob.S3Supported) {\r
+  if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->S3Supported) {\r
     DEBUG ((\r
       DEBUG_ERROR,\r
       "%a: S3Resume2Pei doesn't support X64 PEI + SMM yet.\n",\r
@@ -259,12 +259,13 @@ S3Verification (
  #endif\r
 }\r
 \r
+STATIC\r
 VOID\r
 Q35BoardVerification (\r
-  VOID\r
+  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
   )\r
 {\r
-  if (mPlatformInfoHob.HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
+  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
     return;\r
   }\r
 \r
@@ -273,7 +274,7 @@ Q35BoardVerification (
     "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
     "only DID=0x%04x (Q35) is supported\n",\r
     __FUNCTION__,\r
-    mPlatformInfoHob.HostBridgeDevId,\r
+    PlatformInfoHob->HostBridgeDevId,\r
     INTEL_Q35_MCH_DEVICE_ID\r
     ));\r
   ASSERT (FALSE);\r
@@ -302,12 +303,18 @@ MaxCpuCountInitialization (
 /**\r
  * @brief Builds PlatformInfo Hob\r
  */\r
-VOID\r
+EFI_HOB_PLATFORM_INFO *\r
 BuildPlatformInfoHob (\r
   VOID\r
   )\r
 {\r
-  BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &mPlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO));\r
+  EFI_HOB_PLATFORM_INFO  PlatformInfoHob;\r
+  EFI_HOB_GUID_TYPE      *GuidHob;\r
+\r
+  ZeroMem (&PlatformInfoHob, sizeof PlatformInfoHob);\r
+  BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &PlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO));\r
+  GuidHob = GetFirstGuidHob (&gUefiOvmfPkgPlatformInfoGuid);\r
+  return (EFI_HOB_PLATFORM_INFO *)GET_GUID_HOB_DATA (GuidHob);\r
 }\r
 \r
 /**\r
@@ -326,69 +333,70 @@ InitializePlatform (
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r
-  EFI_STATUS  Status;\r
+  EFI_HOB_PLATFORM_INFO  *PlatformInfoHob;\r
+  EFI_STATUS             Status;\r
 \r
   DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
+  PlatformInfoHob = BuildPlatformInfoHob ();\r
 \r
-  mPlatformInfoHob.SmmSmramRequire     = FeaturePcdGet (PcdSmmSmramRequire);\r
-  mPlatformInfoHob.SevEsIsEnabled      = MemEncryptSevEsIsEnabled ();\r
-  mPlatformInfoHob.PcdPciMmio64Size    = PcdGet64 (PcdPciMmio64Size);\r
-  mPlatformInfoHob.DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
+  PlatformInfoHob->SmmSmramRequire     = FeaturePcdGet (PcdSmmSmramRequire);\r
+  PlatformInfoHob->SevEsIsEnabled      = MemEncryptSevEsIsEnabled ();\r
+  PlatformInfoHob->PcdPciMmio64Size    = PcdGet64 (PcdPciMmio64Size);\r
+  PlatformInfoHob->DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
 \r
   PlatformDebugDumpCmos ();\r
 \r
   if (QemuFwCfgS3Enabled ()) {\r
     DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));\r
-    mPlatformInfoHob.S3Supported = TRUE;\r
+    PlatformInfoHob->S3Supported = TRUE;\r
     Status                       = PcdSetBoolS (PcdAcpiS3Enable, TRUE);\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
 \r
-  S3Verification ();\r
-  BootModeInitialization (&mPlatformInfoHob);\r
+  S3Verification (PlatformInfoHob);\r
+  BootModeInitialization (PlatformInfoHob);\r
 \r
   //\r
   // Query Host Bridge DID\r
   //\r
-  mPlatformInfoHob.HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
-  AddressWidthInitialization (&mPlatformInfoHob);\r
+  PlatformInfoHob->HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
+  AddressWidthInitialization (PlatformInfoHob);\r
 \r
-  MaxCpuCountInitialization (&mPlatformInfoHob);\r
+  MaxCpuCountInitialization (PlatformInfoHob);\r
 \r
-  if (mPlatformInfoHob.SmmSmramRequire) {\r
-    Q35BoardVerification ();\r
-    Q35TsegMbytesInitialization (&mPlatformInfoHob);\r
-    Q35SmramAtDefaultSmbaseInitialization (&mPlatformInfoHob);\r
+  if (PlatformInfoHob->SmmSmramRequire) {\r
+    Q35BoardVerification (PlatformInfoHob);\r
+    Q35TsegMbytesInitialization (PlatformInfoHob);\r
+    Q35SmramAtDefaultSmbaseInitialization (PlatformInfoHob);\r
   }\r
 \r
-  PublishPeiMemory (&mPlatformInfoHob);\r
+  PublishPeiMemory (PlatformInfoHob);\r
 \r
-  PlatformQemuUc32BaseInitialization (&mPlatformInfoHob);\r
+  PlatformQemuUc32BaseInitialization (PlatformInfoHob);\r
 \r
-  InitializeRamRegions (&mPlatformInfoHob);\r
+  InitializeRamRegions (PlatformInfoHob);\r
 \r
-  if (mPlatformInfoHob.BootMode != BOOT_ON_S3_RESUME) {\r
-    if (!mPlatformInfoHob.SmmSmramRequire) {\r
+  if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
+    if (!PlatformInfoHob->SmmSmramRequire) {\r
       ReserveEmuVariableNvStore ();\r
     }\r
 \r
-    PeiFvInitialization (&mPlatformInfoHob);\r
-    MemTypeInfoInitialization ();\r
-    MemMapInitialization (&mPlatformInfoHob);\r
-    NoexecDxeInitialization ();\r
+    PeiFvInitialization (PlatformInfoHob);\r
+    MemTypeInfoInitialization (PlatformInfoHob);\r
+    MemMapInitialization (PlatformInfoHob);\r
+    NoexecDxeInitialization (PlatformInfoHob);\r
   }\r
 \r
   InstallClearCacheCallback ();\r
-  AmdSevInitialize (&mPlatformInfoHob);\r
-  if (mPlatformInfoHob.HostBridgeDevId == 0xffff) {\r
-    MiscInitializationForMicrovm (&mPlatformInfoHob);\r
+  AmdSevInitialize (PlatformInfoHob);\r
+  if (PlatformInfoHob->HostBridgeDevId == 0xffff) {\r
+    MiscInitializationForMicrovm (PlatformInfoHob);\r
   } else {\r
-    MiscInitialization (&mPlatformInfoHob);\r
+    MiscInitialization (PlatformInfoHob);\r
   }\r
 \r
   IntelTdxInitialize ();\r
   InstallFeatureControlCallback ();\r
-  BuildPlatformInfoHob ();\r
 \r
   return EFI_SUCCESS;\r
 }\r