/** @file\r
Header file for Pci shell Debug1 function.\r
\r
+ Copyright (c) 2013 Hewlett-Packard Development Company, L.P.\r
Copyright (c) 2005 - 2010, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
//\r
// Link Capabilities Register\r
//\r
-#define PCIE_CAP_SUP_LINK_SPEEDS(PcieLinkCap) \\r
+#define PCIE_CAP_MAX_LINK_SPEED(PcieLinkCap) \\r
((PcieLinkCap) & 0x0f)\r
#define PCIE_CAP_MAX_LINK_WIDTH(PcieLinkCap) \\r
(((PcieLinkCap) >> 4) & 0x3f)\r
UINT32 SlotCap;\r
UINT16 SlotControl;\r
UINT16 SlotStatus;\r
- UINT16 RsvdP;\r
UINT16 RootControl;\r
+ UINT16 RsvdP;\r
UINT32 RootStatus;\r
-} PCIE_CAP_STURCTURE;\r
+} PCIE_CAP_STRUCTURE;\r
\r
#pragma pack()\r
\r