#include "sysbus.h"
#include "scsi.h"
#include "esp.h"
-
-/* debug ESP card */
-//#define DEBUG_ESP
+#include "trace.h"
/*
* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
*/
-#ifdef DEBUG_ESP
-#define DPRINTF(fmt, ...) \
- do { printf("ESP: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define DPRINTF(fmt, ...) do {} while (0)
-#endif
-
#define ESP_ERROR(fmt, ...) \
do { printf("ESP ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
struct ESPState {
SysBusDevice busdev;
- uint32_t it_shift;
- qemu_irq irq;
+ MemoryRegion iomem;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
+ qemu_irq irq;
+ uint32_t it_shift;
int32_t ti_size;
uint32_t ti_rptr, ti_wptr;
- uint8_t ti_buf[TI_BUFSZ];
uint32_t status;
uint32_t dma;
+ uint8_t ti_buf[TI_BUFSZ];
SCSIBus bus;
SCSIDevice *current_dev;
SCSIRequest *current_req;
/* The size of the current DMA transfer. Zero if no transfer is in
progress. */
uint32_t dma_counter;
- uint8_t *async_buf;
+ int dma_enabled;
+
uint32_t async_len;
+ uint8_t *async_buf;
ESPDMAMemoryReadWriteFunc dma_memory_read;
ESPDMAMemoryReadWriteFunc dma_memory_write;
void *dma_opaque;
- int dma_enabled;
void (*dma_cb)(ESPState *s);
};
if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
s->rregs[ESP_RSTAT] |= STAT_INT;
qemu_irq_raise(s->irq);
- DPRINTF("Raise IRQ\n");
+ trace_esp_raise_irq();
}
}
if (s->rregs[ESP_RSTAT] & STAT_INT) {
s->rregs[ESP_RSTAT] &= ~STAT_INT;
qemu_irq_lower(s->irq);
- DPRINTF("Lower IRQ\n");
+ trace_esp_lower_irq();
}
}
if (level) {
s->dma_enabled = 1;
- DPRINTF("Raise enable\n");
+ trace_esp_dma_enable();
if (s->dma_cb) {
s->dma_cb(s);
s->dma_cb = NULL;
}
} else {
- DPRINTF("Lower enable\n");
+ trace_esp_dma_disable();
s->dma_enabled = 0;
}
}
memcpy(buf, s->ti_buf, dmalen);
buf[0] = buf[2] >> 5;
}
- DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
+ trace_esp_get_cmd(dmalen, target);
s->ti_size = 0;
s->ti_rptr = 0;
s->async_len = 0;
}
- if (target >= ESP_MAX_DEVS || !s->bus.devs[target]) {
+ s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
+ if (!s->current_dev) {
// No such drive
s->rregs[ESP_RSTAT] = 0;
s->rregs[ESP_RINTR] = INTR_DC;
esp_raise_irq(s);
return 0;
}
- s->current_dev = s->bus.devs[target];
return dmalen;
}
{
int32_t datalen;
int lun;
+ SCSIDevice *current_lun;
- DPRINTF("do_busid_cmd: busid 0x%x\n", busid);
+ trace_esp_do_busid_cmd(busid);
lun = busid & 7;
- s->current_req = scsi_req_new(s->current_dev, 0, lun, NULL);
- datalen = scsi_req_enqueue(s->current_req, buf);
+ current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
+ s->current_req = scsi_req_new(current_lun, 0, lun, buf, NULL);
+ datalen = scsi_req_enqueue(s->current_req);
s->ti_size = datalen;
if (datalen != 0) {
s->rregs[ESP_RSTAT] = STAT_TC;
}
s->cmdlen = get_cmd(s, s->cmdbuf);
if (s->cmdlen) {
- DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
+ trace_esp_handle_satn_stop(s->cmdlen);
s->do_cmd = 1;
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
static void write_response(ESPState *s)
{
- DPRINTF("Transfer status (status=%d)\n", s->status);
+ trace_esp_write_response(s->status);
s->ti_buf[0] = s->status;
s->ti_buf[1] = 0;
if (s->dma) {
to_device = (s->ti_size < 0);
len = s->dma_left;
if (s->do_cmd) {
- DPRINTF("command len %d + %d\n", s->cmdlen, len);
+ trace_esp_do_dma(s->cmdlen, len);
s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
s->ti_size = 0;
s->cmdlen = 0;
{
ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
- DPRINTF("SCSI Command complete\n");
+ trace_esp_command_complete();
if (s->ti_size != 0) {
- DPRINTF("SCSI command completed unexpectedly\n");
+ trace_esp_command_complete_unexpected();
}
s->ti_size = 0;
s->dma_left = 0;
s->async_len = 0;
if (status) {
- DPRINTF("Command failed\n");
+ trace_esp_command_complete_fail();
}
s->status = status;
s->rregs[ESP_RSTAT] = STAT_ST;
{
ESPState *s = DO_UPCAST(ESPState, busdev.qdev, req->bus->qbus.parent);
- DPRINTF("transfer %d/%d\n", s->dma_left, s->ti_size);
+ trace_esp_transfer_data(s->dma_left, s->ti_size);
s->async_len = len;
s->async_buf = scsi_req_get_buf(req);
if (s->dma_left) {
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
else
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
- DPRINTF("Transfer Information len %d\n", minlen);
+ trace_esp_handle_ti(minlen);
if (s->dma) {
s->dma_left = minlen;
s->rregs[ESP_RSTAT] &= ~STAT_TC;
esp_do_dma(s);
} else if (s->do_cmd) {
- DPRINTF("command len %d\n", s->cmdlen);
+ trace_esp_handle_ti_cmd(s->cmdlen);
s->ti_size = 0;
s->cmdlen = 0;
s->do_cmd = 0;
}
}
-static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t esp_mem_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
ESPState *s = opaque;
uint32_t saddr, old_val;
saddr = addr >> s->it_shift;
- DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
+ trace_esp_mem_readb(saddr, s->rregs[saddr]);
switch (saddr) {
case ESP_FIFO:
if (s->ti_size > 0) {
return s->rregs[saddr];
}
-static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void esp_mem_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
ESPState *s = opaque;
uint32_t saddr;
saddr = addr >> s->it_shift;
- DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr],
- val);
+ trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
switch (saddr) {
case ESP_TCLO:
case ESP_TCMID:
}
switch(val & CMD_CMD) {
case CMD_NOP:
- DPRINTF("NOP (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_nop(val);
break;
case CMD_FLUSH:
- DPRINTF("Flush FIFO (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_flush(val);
//s->ti_size = 0;
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
break;
case CMD_RESET:
- DPRINTF("Chip reset (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_reset(val);
esp_soft_reset(&s->busdev.qdev);
break;
case CMD_BUSRESET:
- DPRINTF("Bus reset (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_bus_reset(val);
s->rregs[ESP_RINTR] = INTR_RST;
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
esp_raise_irq(s);
handle_ti(s);
break;
case CMD_ICCS:
- DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_iccs(val);
write_response(s);
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSTAT] |= STAT_MI;
break;
case CMD_MSGACC:
- DPRINTF("Message Accepted (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_msgacc(val);
s->rregs[ESP_RINTR] = INTR_DC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;
esp_raise_irq(s);
break;
case CMD_PAD:
- DPRINTF("Transfer padding (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_pad(val);
s->rregs[ESP_RSTAT] = STAT_TC;
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSEQ] = 0;
break;
case CMD_SATN:
- DPRINTF("Set ATN (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_satn(val);
break;
case CMD_SEL:
- DPRINTF("Select without ATN (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_sel(val);
handle_s_without_atn(s);
break;
case CMD_SELATN:
- DPRINTF("Select with ATN (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_selatn(val);
handle_satn(s);
break;
case CMD_SELATNS:
- DPRINTF("Select with ATN & stop (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_selatns(val);
handle_satn_stop(s);
break;
case CMD_ENSEL:
- DPRINTF("Enable selection (%2.2x)\n", val);
+ trace_esp_mem_writeb_cmd_ensel(val);
s->rregs[ESP_RINTR] = 0;
break;
default:
- ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
+ ESP_ERROR("Unhandled ESP command (%2.2x)\n", (unsigned)val);
break;
}
break;
s->rregs[saddr] = val;
break;
default:
- ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
+ ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", (unsigned)val, saddr);
return;
}
s->wregs[saddr] = val;
}
-static CPUReadMemoryFunc * const esp_mem_read[3] = {
- esp_mem_readb,
- NULL,
- NULL,
-};
+static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
+ unsigned size, bool is_write)
+{
+ return (size == 1) || (is_write && size == 4);
+}
-static CPUWriteMemoryFunc * const esp_mem_write[3] = {
- esp_mem_writeb,
- NULL,
- esp_mem_writeb,
+static const MemoryRegionOps esp_mem_ops = {
+ .read = esp_mem_read,
+ .write = esp_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid.accepts = esp_mem_accepts,
};
static const VMStateDescription vmstate_esp = {
*dma_enable = qdev_get_gpio_in(dev, 1);
}
-static const struct SCSIBusOps esp_scsi_ops = {
+static const struct SCSIBusInfo esp_scsi_info = {
+ .tcq = false,
+ .max_target = ESP_MAX_DEVS,
+ .max_lun = 7,
+
.transfer_data = esp_transfer_data,
.complete = esp_command_complete,
.cancel = esp_request_cancelled
static int esp_init1(SysBusDevice *dev)
{
ESPState *s = FROM_SYSBUS(ESPState, dev);
- int esp_io_memory;
sysbus_init_irq(dev, &s->irq);
assert(s->it_shift != -1);
- esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s,
- DEVICE_NATIVE_ENDIAN);
- sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory);
+ memory_region_init_io(&s->iomem, &esp_mem_ops, s,
+ "esp", ESP_REGS << s->it_shift);
+ sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2);
- scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, &esp_scsi_ops);
+ scsi_bus_new(&s->bus, &dev->qdev, &esp_scsi_info);
return scsi_bus_legacy_handle_cmdline(&s->bus);
}
-static SysBusDeviceInfo esp_info = {
- .init = esp_init1,
- .qdev.name = "esp",
- .qdev.size = sizeof(ESPState),
- .qdev.vmsd = &vmstate_esp,
- .qdev.reset = esp_hard_reset,
- .qdev.props = (Property[]) {
- {.name = NULL}
- }
+static Property esp_properties[] = {
+ {.name = NULL},
+};
+
+static void esp_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = esp_init1;
+}
+
+static DeviceInfo esp_info = {
+ .name = "esp",
+ .size = sizeof(ESPState),
+ .vmsd = &vmstate_esp,
+ .reset = esp_hard_reset,
+ .props = esp_properties,
+ .class_init = esp_class_init,
};
static void esp_register_devices(void)
projects / mirror_qemu.git / blobdiff