* The controller is used in Sun4m systems in a slightly different
* way. There are changes in DOR register and DMA is not available.
*/
+
#include "hw.h"
#include "fdc.h"
#include "block.h"
#include "qemu-timer.h"
#include "isa.h"
+#include "sysbus.h"
+#include "qdev-addr.h"
/********************************************************/
/* debug Floppy devices */
//#define DEBUG_FLOPPY
#ifdef DEBUG_FLOPPY
-#define FLOPPY_DPRINTF(fmt, args...) \
-do { printf("FLOPPY: " fmt , ##args); } while (0)
+#define FLOPPY_DPRINTF(fmt, ...) \
+ do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define FLOPPY_DPRINTF(fmt, args...)
+#define FLOPPY_DPRINTF(fmt, ...)
#endif
-#define FLOPPY_ERROR(fmt, args...) \
-do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ##args); } while (0)
+#define FLOPPY_ERROR(fmt, ...) \
+ do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
/********************************************************/
/* Floppy drive emulation */
+#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
+#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
+
/* Will always be a fixed parameter for us */
-#define FD_SECTOR_LEN 512
-#define FD_SECTOR_SC 2 /* Sector size code */
+#define FD_SECTOR_LEN 512
+#define FD_SECTOR_SC 2 /* Sector size code */
+#define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
/* Floppy disk drive emulation */
-typedef enum fdisk_type_t {
+typedef enum FDiskType {
FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
FDRIVE_DISK_USER = 0x04, /* User defined geometry */
FDRIVE_DISK_NONE = 0x05, /* No disk */
-} fdisk_type_t;
+} FDiskType;
-typedef enum fdrive_type_t {
+typedef enum FDriveType {
FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
FDRIVE_DRV_NONE = 0x03, /* No drive connected */
-} fdrive_type_t;
-
-typedef enum fdrive_flags_t {
- FDRIVE_MOTOR_ON = 0x01, /* motor on/off */
-} fdrive_flags_t;
+} FDriveType;
-typedef enum fdisk_flags_t {
+typedef enum FDiskFlags {
FDISK_DBL_SIDES = 0x01,
-} fdisk_flags_t;
+} FDiskFlags;
-typedef struct fdrive_t {
+typedef struct FDrive {
+ DriveInfo *dinfo;
BlockDriverState *bs;
/* Drive status */
- fdrive_type_t drive;
- fdrive_flags_t drflags;
+ FDriveType drive;
uint8_t perpendicular; /* 2.88 MB access mode */
/* Position */
uint8_t head;
uint8_t track;
uint8_t sect;
- /* Last operation status */
- uint8_t dir; /* Direction */
- uint8_t rw; /* Read/write */
/* Media */
- fdisk_flags_t flags;
+ FDiskFlags flags;
uint8_t last_sect; /* Nb sector per track */
uint8_t max_track; /* Nb of tracks */
uint16_t bps; /* Bytes per sector */
uint8_t ro; /* Is read-only */
-} fdrive_t;
+} FDrive;
-static void fd_init (fdrive_t *drv, BlockDriverState *bs)
+static void fd_init(FDrive *drv)
{
/* Drive */
- drv->bs = bs;
+ drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
drv->drive = FDRIVE_DRV_NONE;
- drv->drflags = 0;
drv->perpendicular = 0;
/* Disk */
drv->last_sect = 0;
drv->max_track = 0;
}
-static int _fd_sector (uint8_t head, uint8_t track,
- uint8_t sect, uint8_t last_sect)
+static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
+ uint8_t last_sect)
{
return (((track * 2) + head) * last_sect) + sect - 1;
}
/* Returns current position, in sectors, for given drive */
-static int fd_sector (fdrive_t *drv)
+static int fd_sector(FDrive *drv)
{
- return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
+ return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);
}
-static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
- int enable_seek)
+/* Seek to a new position:
+ * returns 0 if already on right track
+ * returns 1 if track changed
+ * returns 2 if track is invalid
+ * returns 3 if sector is invalid
+ * returns 4 if seek is disabled
+ */
+static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
+ int enable_seek)
{
uint32_t sector;
int ret;
drv->max_track, drv->last_sect);
return 3;
}
- sector = _fd_sector(head, track, sect, drv->last_sect);
+ sector = fd_sector_calc(head, track, sect, drv->last_sect);
ret = 0;
if (sector != fd_sector(drv)) {
#if 0
}
/* Set drive back to track 0 */
-static void fd_recalibrate (fdrive_t *drv)
+static void fd_recalibrate(FDrive *drv)
{
FLOPPY_DPRINTF("recalibrate\n");
drv->head = 0;
drv->track = 0;
drv->sect = 1;
- drv->dir = 1;
- drv->rw = 0;
}
/* Recognize floppy formats */
-typedef struct fd_format_t {
- fdrive_type_t drive;
- fdisk_type_t disk;
+typedef struct FDFormat {
+ FDriveType drive;
+ FDiskType disk;
uint8_t last_sect;
uint8_t max_track;
uint8_t max_head;
const char *str;
-} fd_format_t;
+} FDFormat;
-static const fd_format_t fd_formats[] = {
+static const FDFormat fd_formats[] = {
/* First entry is default format */
/* 1.44 MB 3"1/2 floppy disks */
{ FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
};
/* Revalidate a disk drive after a disk change */
-static void fd_revalidate (fdrive_t *drv)
+static void fd_revalidate(FDrive *drv)
{
- const fd_format_t *parse;
+ const FDFormat *parse;
uint64_t nb_sectors, size;
int i, first_match, match;
int nb_heads, max_track, last_sect, ro;
}
}
-/* Motor control */
-static void fd_start (fdrive_t *drv)
-{
- drv->drflags |= FDRIVE_MOTOR_ON;
-}
-
-static void fd_stop (fdrive_t *drv)
-{
- drv->drflags &= ~FDRIVE_MOTOR_ON;
-}
-
-/* Re-initialise a drives (motor off, repositioned) */
-static void fd_reset (fdrive_t *drv)
-{
- fd_stop(drv);
- fd_recalibrate(drv);
-}
-
/********************************************************/
/* Intel 82078 floppy disk controller emulation */
-static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
-static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
+static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
+static void fdctrl_reset_fifo(FDCtrl *fdctrl);
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len);
-static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status);
-
-static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
-static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
-static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
-static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
-static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
-static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
-static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
-static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
-
-enum {
- FD_CTRL_ACTIVE = 0x01, /* XXX: suppress that */
- FD_CTRL_RESET = 0x02,
- FD_CTRL_SLEEP = 0x04, /* XXX: suppress that */
- FD_CTRL_BUSY = 0x08, /* dma transfer in progress */
-};
+static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
+
+static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
+static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
+static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
+static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
+static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
+static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
+static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
+static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
enum {
FD_DIR_WRITE = 0,
};
enum {
- FD_STATE_CMD = 0x00,
- FD_STATE_STATUS = 0x01,
- FD_STATE_DATA = 0x02,
- FD_STATE_STATE = 0x03,
- FD_STATE_MULTI = 0x10,
- FD_STATE_SEEK = 0x20,
- FD_STATE_FORMAT = 0x40,
+ FD_STATE_MULTI = 0x01, /* multi track flag */
+ FD_STATE_FORMAT = 0x02, /* format flag */
+ FD_STATE_SEEK = 0x04, /* seek flag */
};
enum {
FD_SR0_RDYCHG = 0xc0,
};
+enum {
+ FD_SR1_EC = 0x80, /* End of cylinder */
+};
+
+enum {
+ FD_SR2_SNS = 0x04, /* Scan not satisfied */
+ FD_SR2_SEH = 0x08, /* Scan equal hit */
+};
+
enum {
FD_SRA_DIR = 0x01,
FD_SRA_nWP = 0x02,
};
enum {
+#if MAX_FD == 4
+ FD_DOR_SELMASK = 0x03,
+#else
FD_DOR_SELMASK = 0x01,
+#endif
FD_DOR_nRESET = 0x04,
FD_DOR_DMAEN = 0x08,
FD_DOR_MOTEN0 = 0x10,
};
enum {
+#if MAX_FD == 4
FD_TDR_BOOTSEL = 0x0c,
+#else
+ FD_TDR_BOOTSEL = 0x04,
+#endif
};
enum {
FD_DIR_DSKCHG = 0x80,
};
-#define FD_STATE(state) ((state) & FD_STATE_STATE)
-#define FD_SET_STATE(state, new_state) \
-do { (state) = ((state) & ~FD_STATE_STATE) | (new_state); } while (0)
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
-struct fdctrl_t {
- fdctrl_t *fdctrl;
+struct FDCtrl {
/* Controller's identification */
uint8_t version;
/* HW */
qemu_irq irq;
int dma_chann;
- target_phys_addr_t io_base;
/* Controller state */
QEMUTimer *result_timer;
uint8_t sra;
uint8_t srb;
- uint8_t state;
- uint8_t dma_en;
+ uint8_t dor;
+ uint8_t dor_vmstate; /* only used as temp during vmstate */
+ uint8_t tdr;
+ uint8_t dsr;
+ uint8_t msr;
uint8_t cur_drv;
- uint8_t bootsel;
+ uint8_t status0;
+ uint8_t status1;
+ uint8_t status2;
/* Command FIFO */
uint8_t *fifo;
+ int32_t fifo_size;
uint32_t data_pos;
uint32_t data_len;
uint8_t data_state;
uint8_t data_dir;
- uint8_t int_status;
uint8_t eot; /* last wanted sector */
/* States kept only to be returned back */
/* Timers state */
/* Sun4m quirks? */
int sun4m;
/* Floppy drives */
- fdrive_t drives[2];
+ uint8_t num_floppies;
+ FDrive drives[MAX_FD];
+ int reset_sensei;
};
+typedef struct FDCtrlSysBus {
+ SysBusDevice busdev;
+ struct FDCtrl state;
+} FDCtrlSysBus;
+
+typedef struct FDCtrlISABus {
+ ISADevice busdev;
+ struct FDCtrl state;
+} FDCtrlISABus;
+
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
{
- fdctrl_t *fdctrl = opaque;
+ FDCtrl *fdctrl = opaque;
uint32_t retval;
- switch (reg & 0x07) {
+ switch (reg) {
case FD_REG_SRA:
retval = fdctrl_read_statusA(fdctrl);
break;
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
{
- fdctrl_t *fdctrl = opaque;
+ FDCtrl *fdctrl = opaque;
FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
- switch (reg & 0x07) {
+ switch (reg) {
case FD_REG_DOR:
fdctrl_write_dor(fdctrl, value);
break;
}
}
+static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
+{
+ return fdctrl_read(opaque, reg & 7);
+}
+
+static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
+{
+ fdctrl_write(opaque, reg & 7, value);
+}
+
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
{
return fdctrl_read(opaque, (uint32_t)reg);
fdctrl_write(opaque, (uint32_t)reg, value);
}
-static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
+static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
fdctrl_read_mem,
fdctrl_read_mem,
fdctrl_read_mem,
};
-static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
+static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
fdctrl_write_mem,
fdctrl_write_mem,
fdctrl_write_mem,
};
-static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
+static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
fdctrl_read_mem,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
+static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
fdctrl_write_mem,
NULL,
NULL,
};
-static void fd_save (QEMUFile *f, fdrive_t *fd)
+static const VMStateDescription vmstate_fdrive = {
+ .name = "fdrive",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(head, FDrive),
+ VMSTATE_UINT8(track, FDrive),
+ VMSTATE_UINT8(sect, FDrive),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void fdc_pre_save(void *opaque)
{
- uint8_t tmp;
+ FDCtrl *s = opaque;
- tmp = fd->drflags;
- qemu_put_8s(f, &tmp);
- qemu_put_8s(f, &fd->head);
- qemu_put_8s(f, &fd->track);
- qemu_put_8s(f, &fd->sect);
- qemu_put_8s(f, &fd->dir);
- qemu_put_8s(f, &fd->rw);
+ s->dor_vmstate = s->dor | GET_CUR_DRV(s);
}
-static void fdc_save (QEMUFile *f, void *opaque)
+static int fdc_post_load(void *opaque, int version_id)
{
- fdctrl_t *s = opaque;
-
- /* Controller state */
- qemu_put_8s(f, &s->sra);
- qemu_put_8s(f, &s->srb);
- qemu_put_8s(f, &s->state);
- qemu_put_8s(f, &s->dma_en);
- qemu_put_8s(f, &s->cur_drv);
- qemu_put_8s(f, &s->bootsel);
- qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
- qemu_put_be32s(f, &s->data_pos);
- qemu_put_be32s(f, &s->data_len);
- qemu_put_8s(f, &s->data_state);
- qemu_put_8s(f, &s->data_dir);
- qemu_put_8s(f, &s->int_status);
- qemu_put_8s(f, &s->eot);
- qemu_put_8s(f, &s->timer0);
- qemu_put_8s(f, &s->timer1);
- qemu_put_8s(f, &s->precomp_trk);
- qemu_put_8s(f, &s->config);
- qemu_put_8s(f, &s->lock);
- qemu_put_8s(f, &s->pwrd);
- fd_save(f, &s->drives[0]);
- fd_save(f, &s->drives[1]);
-}
-
-static int fd_load (QEMUFile *f, fdrive_t *fd)
-{
- uint8_t tmp;
-
- qemu_get_8s(f, &tmp);
- fd->drflags = tmp;
- qemu_get_8s(f, &fd->head);
- qemu_get_8s(f, &fd->track);
- qemu_get_8s(f, &fd->sect);
- qemu_get_8s(f, &fd->dir);
- qemu_get_8s(f, &fd->rw);
+ FDCtrl *s = opaque;
+ SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
+ s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
return 0;
}
-static int fdc_load (QEMUFile *f, void *opaque, int version_id)
-{
- fdctrl_t *s = opaque;
- int ret;
-
- if (version_id != 1)
- return -EINVAL;
+static const VMStateDescription vmstate_fdc = {
+ .name = "fdc",
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .minimum_version_id_old = 2,
+ .pre_save = fdc_pre_save,
+ .post_load = fdc_post_load,
+ .fields = (VMStateField []) {
+ /* Controller State */
+ VMSTATE_UINT8(sra, FDCtrl),
+ VMSTATE_UINT8(srb, FDCtrl),
+ VMSTATE_UINT8(dor_vmstate, FDCtrl),
+ VMSTATE_UINT8(tdr, FDCtrl),
+ VMSTATE_UINT8(dsr, FDCtrl),
+ VMSTATE_UINT8(msr, FDCtrl),
+ VMSTATE_UINT8(status0, FDCtrl),
+ VMSTATE_UINT8(status1, FDCtrl),
+ VMSTATE_UINT8(status2, FDCtrl),
+ /* Command FIFO */
+ VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
+ uint8_t),
+ VMSTATE_UINT32(data_pos, FDCtrl),
+ VMSTATE_UINT32(data_len, FDCtrl),
+ VMSTATE_UINT8(data_state, FDCtrl),
+ VMSTATE_UINT8(data_dir, FDCtrl),
+ VMSTATE_UINT8(eot, FDCtrl),
+ /* States kept only to be returned back */
+ VMSTATE_UINT8(timer0, FDCtrl),
+ VMSTATE_UINT8(timer1, FDCtrl),
+ VMSTATE_UINT8(precomp_trk, FDCtrl),
+ VMSTATE_UINT8(config, FDCtrl),
+ VMSTATE_UINT8(lock, FDCtrl),
+ VMSTATE_UINT8(pwrd, FDCtrl),
+ VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
+ VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
+ vmstate_fdrive, FDrive),
+ VMSTATE_END_OF_LIST()
+ }
+};
- /* Controller state */
- qemu_get_8s(f, &s->sra);
- qemu_get_8s(f, &s->srb);
- qemu_get_8s(f, &s->state);
- qemu_get_8s(f, &s->dma_en);
- qemu_get_8s(f, &s->cur_drv);
- qemu_get_8s(f, &s->bootsel);
- qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
- qemu_get_be32s(f, &s->data_pos);
- qemu_get_be32s(f, &s->data_len);
- qemu_get_8s(f, &s->data_state);
- qemu_get_8s(f, &s->data_dir);
- qemu_get_8s(f, &s->int_status);
- qemu_get_8s(f, &s->eot);
- qemu_get_8s(f, &s->timer0);
- qemu_get_8s(f, &s->timer1);
- qemu_get_8s(f, &s->precomp_trk);
- qemu_get_8s(f, &s->config);
- qemu_get_8s(f, &s->lock);
- qemu_get_8s(f, &s->pwrd);
-
- ret = fd_load(f, &s->drives[0]);
- if (ret == 0)
- ret = fd_load(f, &s->drives[1]);
+static void fdctrl_external_reset_sysbus(DeviceState *d)
+{
+ FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
+ FDCtrl *s = &sys->state;
- return ret;
+ fdctrl_reset(s, 0);
}
-static void fdctrl_external_reset(void *opaque)
+static void fdctrl_external_reset_isa(DeviceState *d)
{
- fdctrl_t *s = opaque;
+ FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
+ FDCtrl *s = &isa->state;
fdctrl_reset(s, 0);
}
static void fdctrl_handle_tc(void *opaque, int irq, int level)
{
- //fdctrl_t *s = opaque;
+ //FDCtrl *s = opaque;
if (level) {
// XXX
}
/* XXX: may change if moved to bdrv */
-int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
+int fdctrl_get_drive_type(FDCtrl *fdctrl, int drive_num)
{
return fdctrl->drives[drive_num].drive;
}
/* Change IRQ state */
-static void fdctrl_reset_irq (fdctrl_t *fdctrl)
+static void fdctrl_reset_irq(FDCtrl *fdctrl)
{
if (!(fdctrl->sra & FD_SRA_INTPEND))
return;
fdctrl->sra &= ~FD_SRA_INTPEND;
}
-static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status)
+static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
{
- // Sparc mutation
- if (fdctrl->sun4m && !fdctrl->dma_en) {
- fdctrl->state &= ~FD_CTRL_BUSY;
- fdctrl->int_status = status;
+ /* Sparc mutation */
+ if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
+ /* XXX: not sure */
+ fdctrl->msr &= ~FD_MSR_CMDBUSY;
+ fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
+ fdctrl->status0 = status0;
return;
}
if (!(fdctrl->sra & FD_SRA_INTPEND)) {
qemu_set_irq(fdctrl->irq, 1);
fdctrl->sra |= FD_SRA_INTPEND;
}
- FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", status);
- fdctrl->int_status = status;
+ fdctrl->reset_sensei = 0;
+ fdctrl->status0 = status0;
+ FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
}
/* Reset controller */
-static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
+static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
{
int i;
if (!fdctrl->drives[1].bs)
fdctrl->sra |= FD_SRA_nDRV2;
fdctrl->cur_drv = 0;
+ fdctrl->dor = FD_DOR_nRESET;
+ fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
+ fdctrl->msr = FD_MSR_RQM;
/* FIFO state */
fdctrl->data_pos = 0;
fdctrl->data_len = 0;
- fdctrl->data_state = FD_STATE_CMD;
+ fdctrl->data_state = 0;
fdctrl->data_dir = FD_DIR_WRITE;
for (i = 0; i < MAX_FD; i++)
- fd_reset(&fdctrl->drives[i]);
+ fd_recalibrate(&fdctrl->drives[i]);
fdctrl_reset_fifo(fdctrl);
- if (do_irq)
+ if (do_irq) {
fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
+ fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
+ }
+}
+
+static inline FDrive *drv0(FDCtrl *fdctrl)
+{
+ return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
}
-static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
+static inline FDrive *drv1(FDCtrl *fdctrl)
{
- return &fdctrl->drives[fdctrl->bootsel];
+ if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
+ return &fdctrl->drives[1];
+ else
+ return &fdctrl->drives[0];
}
-static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
+#if MAX_FD == 4
+static inline FDrive *drv2(FDCtrl *fdctrl)
{
- return &fdctrl->drives[1 - fdctrl->bootsel];
+ if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
+ return &fdctrl->drives[2];
+ else
+ return &fdctrl->drives[1];
}
-static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
+static inline FDrive *drv3(FDCtrl *fdctrl)
{
- return fdctrl->cur_drv == 0 ? drv0(fdctrl) : drv1(fdctrl);
+ if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
+ return &fdctrl->drives[3];
+ else
+ return &fdctrl->drives[2];
+}
+#endif
+
+static FDrive *get_cur_drv(FDCtrl *fdctrl)
+{
+ switch (fdctrl->cur_drv) {
+ case 0: return drv0(fdctrl);
+ case 1: return drv1(fdctrl);
+#if MAX_FD == 4
+ case 2: return drv2(fdctrl);
+ case 3: return drv3(fdctrl);
+#endif
+ default: return NULL;
+ }
}
/* Status A register : 0x00 (read-only) */
-static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
{
uint32_t retval = fdctrl->sra;
}
/* Status B register : 0x01 (read-only) */
-static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
{
uint32_t retval = fdctrl->srb;
}
/* Digital output register : 0x02 */
-static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
{
- uint32_t retval = 0;
+ uint32_t retval = fdctrl->dor;
- /* Drive motors state indicators */
- if (drv0(fdctrl)->drflags & FDRIVE_MOTOR_ON)
- retval |= FD_DOR_MOTEN0;
- if (drv1(fdctrl)->drflags & FDRIVE_MOTOR_ON)
- retval |= FD_DOR_MOTEN1;
- /* DMA enable */
- if (fdctrl->dma_en)
- retval |= FD_DOR_DMAEN;
- /* Reset indicator */
- if (!(fdctrl->state & FD_CTRL_RESET))
- retval |= FD_DOR_nRESET;
/* Selected drive */
retval |= fdctrl->cur_drv;
FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
return retval;
}
-static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
{
- /* Reset mode */
- if (fdctrl->state & FD_CTRL_RESET) {
- if (!(value & FD_DOR_nRESET)) {
- FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
- return;
- }
- }
FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
/* Motors */
else
fdctrl->srb &= ~FD_SRB_DR0;
- /* Drive motors state indicators */
- if (value & FD_DOR_MOTEN1)
- fd_start(drv1(fdctrl));
- else
- fd_stop(drv1(fdctrl));
- if (value & FD_DOR_MOTEN0)
- fd_start(drv0(fdctrl));
- else
- fd_stop(drv0(fdctrl));
- /* DMA enable */
-#if 0
- if (fdctrl->dma_chann != -1)
- fdctrl->dma_en = value & FD_DOR_DMAEN ? 1 : 0;
-#endif
/* Reset */
if (!(value & FD_DOR_nRESET)) {
- if (!(fdctrl->state & FD_CTRL_RESET)) {
+ if (fdctrl->dor & FD_DOR_nRESET) {
FLOPPY_DPRINTF("controller enter RESET state\n");
- fdctrl->state |= FD_CTRL_RESET;
}
} else {
- if (fdctrl->state & FD_CTRL_RESET) {
+ if (!(fdctrl->dor & FD_DOR_nRESET)) {
FLOPPY_DPRINTF("controller out of RESET state\n");
fdctrl_reset(fdctrl, 1);
- fdctrl->state &= ~(FD_CTRL_RESET | FD_CTRL_SLEEP);
+ fdctrl->dsr &= ~FD_DSR_PWRDOWN;
}
}
/* Selected drive */
fdctrl->cur_drv = value & FD_DOR_SELMASK;
+
+ fdctrl->dor = value;
}
/* Tape drive register : 0x03 */
-static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
{
- uint32_t retval = 0;
+ uint32_t retval = fdctrl->tdr;
- /* Disk boot selection indicator */
- retval |= fdctrl->bootsel << 2;
- /* Tape indicators: never allowed */
FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
return retval;
}
-static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
{
/* Reset mode */
- if (fdctrl->state & FD_CTRL_RESET) {
+ if (!(fdctrl->dor & FD_DOR_nRESET)) {
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
return;
}
FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
/* Disk boot selection indicator */
- fdctrl->bootsel = (value & FD_TDR_BOOTSEL) >> 2;
+ fdctrl->tdr = value & FD_TDR_BOOTSEL;
/* Tape indicators: never allow */
}
/* Main status register : 0x04 (read) */
-static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
{
- uint32_t retval = 0;
+ uint32_t retval = fdctrl->msr;
+
+ fdctrl->dsr &= ~FD_DSR_PWRDOWN;
+ fdctrl->dor |= FD_DOR_nRESET;
+
+ /* Sparc mutation */
+ if (fdctrl->sun4m) {
+ retval |= FD_MSR_DIO;
+ fdctrl_reset_irq(fdctrl);
+ };
- fdctrl->state &= ~(FD_CTRL_SLEEP | FD_CTRL_RESET);
- if (!(fdctrl->state & FD_CTRL_BUSY)) {
- /* Data transfer allowed */
- retval |= FD_MSR_RQM;
- /* Data transfer direction indicator */
- if (fdctrl->data_dir == FD_DIR_READ)
- retval |= FD_MSR_DIO;
- }
- /* Should handle FD_MSR_NONDMA for SPECIFY command */
- /* Command busy indicator */
- if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA ||
- FD_STATE(fdctrl->data_state) == FD_STATE_STATUS)
- retval |= FD_MSR_CMDBUSY;
FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
return retval;
}
/* Data select rate register : 0x04 (write) */
-static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
{
/* Reset mode */
- if (fdctrl->state & FD_CTRL_RESET) {
+ if (!(fdctrl->dor & FD_DOR_nRESET)) {
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
return;
}
FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
/* Reset: autoclear */
if (value & FD_DSR_SWRESET) {
- fdctrl->state |= FD_CTRL_RESET;
+ fdctrl->dor &= ~FD_DOR_nRESET;
fdctrl_reset(fdctrl, 1);
- fdctrl->state &= ~FD_CTRL_RESET;
+ fdctrl->dor |= FD_DOR_nRESET;
}
if (value & FD_DSR_PWRDOWN) {
- fdctrl->state |= FD_CTRL_SLEEP;
fdctrl_reset(fdctrl, 1);
}
+ fdctrl->dsr = value;
}
-static int fdctrl_media_changed(fdrive_t *drv)
+static int fdctrl_media_changed(FDrive *drv)
{
int ret;
}
/* Digital input register : 0x07 (read-only) */
-static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
{
uint32_t retval = 0;
- if (fdctrl_media_changed(drv0(fdctrl)) ||
- fdctrl_media_changed(drv1(fdctrl)))
+ if (fdctrl_media_changed(drv0(fdctrl))
+ || fdctrl_media_changed(drv1(fdctrl))
+#if MAX_FD == 4
+ || fdctrl_media_changed(drv2(fdctrl))
+ || fdctrl_media_changed(drv3(fdctrl))
+#endif
+ )
retval |= FD_DIR_DSKCHG;
if (retval != 0)
FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
}
/* FIFO state control */
-static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
+static void fdctrl_reset_fifo(FDCtrl *fdctrl)
{
fdctrl->data_dir = FD_DIR_WRITE;
fdctrl->data_pos = 0;
- FD_SET_STATE(fdctrl->data_state, FD_STATE_CMD);
+ fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
}
/* Set FIFO status for the host to read */
-static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
+static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
{
fdctrl->data_dir = FD_DIR_READ;
fdctrl->data_len = fifo_len;
fdctrl->data_pos = 0;
- FD_SET_STATE(fdctrl->data_state, FD_STATE_STATUS);
+ fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
if (do_irq)
fdctrl_raise_irq(fdctrl, 0x00);
}
/* Set an error: unimplemented/unknown command */
-static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
+static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
{
-#if 0
- fdrive_t *cur_drv;
-
- cur_drv = get_cur_drv(fdctrl);
- fdctrl->fifo[0] = FD_SR0_ABNTERM | FD_SR0_SEEK | (cur_drv->head << 2) | fdctrl->cur_drv;
- fdctrl->fifo[1] = 0x00;
- fdctrl->fifo[2] = 0x00;
- fdctrl_set_fifo(fdctrl, 3, 1);
-#else
- // fdctrl_reset_fifo(fdctrl);
+ FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
fdctrl->fifo[0] = FD_SR0_INVCMD;
fdctrl_set_fifo(fdctrl, 1, 0);
-#endif
}
/* Seek to next sector */
-static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
+static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
{
FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
cur_drv->head, cur_drv->track, cur_drv->sect,
}
/* Callback for transfer end (stop or abort) */
-static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
- uint8_t status1, uint8_t status2)
+static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
+ uint8_t status1, uint8_t status2)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
cur_drv = get_cur_drv(fdctrl);
FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
status0, status1, status2,
- status0 | (cur_drv->head << 2) | fdctrl->cur_drv);
- fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | fdctrl->cur_drv;
+ status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
+ fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
fdctrl->fifo[1] = status1;
fdctrl->fifo[2] = status2;
fdctrl->fifo[3] = cur_drv->track;
fdctrl->fifo[5] = cur_drv->sect;
fdctrl->fifo[6] = FD_SECTOR_SC;
fdctrl->data_dir = FD_DIR_READ;
- if (fdctrl->state & FD_CTRL_BUSY) {
+ if (!(fdctrl->msr & FD_MSR_NONDMA)) {
DMA_release_DREQ(fdctrl->dma_chann);
- fdctrl->state &= ~FD_CTRL_BUSY;
}
+ fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
+ fdctrl->msr &= ~FD_MSR_NONDMA;
fdctrl_set_fifo(fdctrl, 7, 1);
}
/* Prepare a data transfer (either DMA or FIFO) */
-static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
+static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
uint8_t kh, kt, ks;
- int did_seek;
+ int did_seek = 0;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
kt = fdctrl->fifo[2];
kh = fdctrl->fifo[3];
ks = fdctrl->fifo[4];
FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
- fdctrl->cur_drv, kh, kt, ks,
- _fd_sector(kh, kt, ks, cur_drv->last_sect));
- did_seek = 0;
- switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & 0x40)) {
+ GET_CUR_DRV(fdctrl), kh, kt, ks,
+ fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
+ switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
case 2:
/* sect too big */
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
return;
case 3:
/* track too big */
- fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x80, 0x00);
+ fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
fdctrl->fifo[3] = kt;
fdctrl->fifo[4] = kh;
fdctrl->fifo[5] = ks;
default:
break;
}
+
/* Set the FIFO state */
fdctrl->data_dir = direction;
fdctrl->data_pos = 0;
- FD_SET_STATE(fdctrl->data_state, FD_STATE_DATA); /* FIFO ready for data */
+ fdctrl->msr |= FD_MSR_CMDBUSY;
if (fdctrl->fifo[0] & 0x80)
fdctrl->data_state |= FD_STATE_MULTI;
else
} else {
int tmp;
fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
- tmp = (cur_drv->last_sect - ks + 1);
+ tmp = (fdctrl->fifo[6] - ks + 1);
if (fdctrl->fifo[0] & 0x80)
- tmp += cur_drv->last_sect;
+ tmp += fdctrl->fifo[6];
fdctrl->data_len *= tmp;
}
fdctrl->eot = fdctrl->fifo[6];
- if (fdctrl->dma_en) {
+ if (fdctrl->dor & FD_DOR_DMAEN) {
int dma_mode;
/* DMA transfer are enabled. Check if DMA channel is well programmed */
dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
(direction == FD_DIR_WRITE && dma_mode == 2) ||
(direction == FD_DIR_READ && dma_mode == 1)) {
/* No access is allowed until DMA transfer has completed */
- fdctrl->state |= FD_CTRL_BUSY;
+ fdctrl->msr &= ~FD_MSR_RQM;
/* Now, we just have to wait for the DMA controller to
* recall us...
*/
}
}
FLOPPY_DPRINTF("start non-DMA transfer\n");
+ fdctrl->msr |= FD_MSR_NONDMA;
+ if (direction != FD_DIR_WRITE)
+ fdctrl->msr |= FD_MSR_DIO;
/* IO based transfer: calculate len */
fdctrl_raise_irq(fdctrl, 0x00);
}
/* Prepare a transfer of deleted data */
-static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
+static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
{
+ FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
+
/* We don't handle deleted data,
* so we don't return *ANYTHING*
*/
static int fdctrl_transfer_handler (void *opaque, int nchan,
int dma_pos, int dma_len)
{
- fdctrl_t *fdctrl;
- fdrive_t *cur_drv;
+ FDCtrl *fdctrl;
+ FDrive *cur_drv;
int len, start_pos, rel_pos;
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
fdctrl = opaque;
- if (!(fdctrl->state & FD_CTRL_BUSY)) {
+ if (fdctrl->msr & FD_MSR_RQM) {
FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
return 0;
}
cur_drv = get_cur_drv(fdctrl);
if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
fdctrl->data_dir == FD_DIR_SCANH)
- status2 = 0x04;
+ status2 = FD_SR2_SNS;
if (dma_len > fdctrl->data_len)
dma_len = fdctrl->data_len;
if (cur_drv->bs == NULL) {
len = FD_SECTOR_LEN - rel_pos;
FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
"(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
- fdctrl->data_len, fdctrl->cur_drv, cur_drv->head,
+ fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
fd_sector(cur_drv) * FD_SECTOR_LEN);
if (fdctrl->data_dir != FD_DIR_WRITE ||
fdctrl->data_pos, len);
if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
fdctrl->fifo, 1) < 0) {
- FLOPPY_ERROR("writting sector %d\n", fd_sector(cur_drv));
+ FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
goto transfer_error;
}
DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
if (ret == 0) {
- status2 = 0x08;
+ status2 = FD_SR2_SEH;
goto end_transfer;
}
if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
if (fdctrl->data_dir == FD_DIR_SCANE ||
fdctrl->data_dir == FD_DIR_SCANL ||
fdctrl->data_dir == FD_DIR_SCANH)
- status2 = 0x08;
+ status2 = FD_SR2_SEH;
if (FD_DID_SEEK(fdctrl->data_state))
status0 |= FD_SR0_SEEK;
fdctrl->data_len -= len;
- // if (fdctrl->data_len == 0)
fdctrl_stop_transfer(fdctrl, status0, status1, status2);
transfer_error:
}
/* Data register : 0x05 */
-static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
+static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
uint32_t retval = 0;
int pos;
cur_drv = get_cur_drv(fdctrl);
- fdctrl->state &= ~FD_CTRL_SLEEP;
- if (FD_STATE(fdctrl->data_state) == FD_STATE_CMD) {
- FLOPPY_ERROR("can't read data in CMD state\n");
+ fdctrl->dsr &= ~FD_DSR_PWRDOWN;
+ if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
+ FLOPPY_ERROR("controller not ready for reading\n");
return 0;
}
pos = fdctrl->data_pos;
- if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
+ if (fdctrl->msr & FD_MSR_NONDMA) {
pos %= FD_SECTOR_LEN;
if (pos == 0) {
if (fdctrl->data_pos != 0)
fd_sector(cur_drv));
return 0;
}
- bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1);
+ if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
+ FLOPPY_DPRINTF("error getting sector %d\n",
+ fd_sector(cur_drv));
+ /* Sure, image size is too small... */
+ memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
+ }
}
}
retval = fdctrl->fifo[pos];
/* Switch from transfer mode to status mode
* then from status mode to command mode
*/
- if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
+ if (fdctrl->msr & FD_MSR_NONDMA) {
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
} else {
fdctrl_reset_fifo(fdctrl);
return retval;
}
-static void fdctrl_format_sector (fdctrl_t *fdctrl)
+static void fdctrl_format_sector(FDCtrl *fdctrl)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
uint8_t kh, kt, ks;
- int did_seek;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
kt = fdctrl->fifo[6];
kh = fdctrl->fifo[7];
ks = fdctrl->fifo[8];
FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
- fdctrl->cur_drv, kh, kt, ks,
- _fd_sector(kh, kt, ks, cur_drv->last_sect));
- did_seek = 0;
+ GET_CUR_DRV(fdctrl), kh, kt, ks,
+ fd_sector_calc(kh, kt, ks, cur_drv->last_sect));
switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
case 2:
/* sect too big */
return;
case 3:
/* track too big */
- fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x80, 0x00);
+ fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
fdctrl->fifo[3] = kt;
fdctrl->fifo[4] = kh;
fdctrl->fifo[5] = ks;
fdctrl->fifo[5] = ks;
return;
case 1:
- did_seek = 1;
fdctrl->data_state |= FD_STATE_SEEK;
break;
default:
}
}
-static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
{
fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
fdctrl->fifo[0] = fdctrl->lock << 4;
fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
}
-static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
fdctrl->fifo[0] = drv0(fdctrl)->track;
fdctrl->fifo[1] = drv1(fdctrl)->track;
+#if MAX_FD == 4
+ fdctrl->fifo[2] = drv2(fdctrl)->track;
+ fdctrl->fifo[3] = drv3(fdctrl)->track;
+#else
fdctrl->fifo[2] = 0;
fdctrl->fifo[3] = 0;
+#endif
/* timers */
fdctrl->fifo[4] = fdctrl->timer0;
- fdctrl->fifo[5] = (fdctrl->timer1 << 1) | fdctrl->dma_en;
+ fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
fdctrl->fifo[6] = cur_drv->last_sect;
fdctrl->fifo[7] = (fdctrl->lock << 7) |
(cur_drv->perpendicular << 2);
fdctrl_set_fifo(fdctrl, 10, 0);
}
-static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
{
/* Controller's version */
fdctrl->fifo[0] = fdctrl->version;
fdctrl_set_fifo(fdctrl, 1, 1);
}
-static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
{
fdctrl->fifo[0] = 0x41; /* Stepping 1 */
fdctrl_set_fifo(fdctrl, 1, 0);
}
-static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* Drives position */
drv0(fdctrl)->track = fdctrl->fifo[3];
drv1(fdctrl)->track = fdctrl->fifo[4];
+#if MAX_FD == 4
+ drv2(fdctrl)->track = fdctrl->fifo[5];
+ drv3(fdctrl)->track = fdctrl->fifo[6];
+#endif
/* timers */
fdctrl->timer0 = fdctrl->fifo[7];
fdctrl->timer1 = fdctrl->fifo[8];
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
fdctrl->fifo[0] = 0;
fdctrl->fifo[1] = 0;
/* Drives position */
fdctrl->fifo[2] = drv0(fdctrl)->track;
fdctrl->fifo[3] = drv1(fdctrl)->track;
+#if MAX_FD == 4
+ fdctrl->fifo[4] = drv2(fdctrl)->track;
+ fdctrl->fifo[5] = drv3(fdctrl)->track;
+#else
fdctrl->fifo[4] = 0;
fdctrl->fifo[5] = 0;
+#endif
/* timers */
fdctrl->fifo[6] = fdctrl->timer0;
fdctrl->fifo[7] = fdctrl->timer1;
fdctrl_set_fifo(fdctrl, 15, 1);
}
-static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* XXX: should set main status register to busy */
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
qemu_mod_timer(fdctrl->result_timer,
- qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
+ qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
}
-static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fdctrl->data_state |= FD_STATE_FORMAT;
if (fdctrl->fifo[0] & 0x80)
fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
}
-static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
{
fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
fdctrl->timer1 = fdctrl->fifo[2] >> 1;
- fdctrl->dma_en = 1 - (fdctrl->fifo[2] & 1) ;
+ if (fdctrl->fifo[2] & 1)
+ fdctrl->dor &= ~FD_DOR_DMAEN;
+ else
+ fdctrl->dor |= FD_DOR_DMAEN;
/* No result back */
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
/* 1 Byte status back */
fdctrl->fifo[0] = (cur_drv->ro << 6) |
(cur_drv->track == 0 ? 0x10 : 0x00) |
(cur_drv->head << 2) |
- fdctrl->cur_drv |
+ GET_CUR_DRV(fdctrl) |
0x28;
fdctrl_set_fifo(fdctrl, 1, 0);
}
-static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
fd_recalibrate(cur_drv);
fdctrl_reset_fifo(fdctrl);
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
-static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
+
+ if(fdctrl->reset_sensei > 0) {
+ fdctrl->fifo[0] =
+ FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
+ fdctrl->reset_sensei--;
+ } else {
+ /* XXX: status0 handling is broken for read/write
+ commands, so we do this hack. It should be suppressed
+ ASAP */
+ fdctrl->fifo[0] =
+ FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
+ }
-#if 0
- fdctrl->fifo[0] =
- fdctrl->int_status | (cur_drv->head << 2) | fdctrl->cur_drv;
-#else
- /* XXX: int_status handling is broken for read/write
- commands, so we do this hack. It should be suppressed
- ASAP */
- fdctrl->fifo[0] =
- 0x20 | (cur_drv->head << 2) | fdctrl->cur_drv;
-#endif
fdctrl->fifo[1] = cur_drv->track;
fdctrl_set_fifo(fdctrl, 2, 0);
fdctrl_reset_irq(fdctrl);
- fdctrl->int_status = FD_SR0_RDYCHG;
+ fdctrl->status0 = FD_SR0_RDYCHG;
}
-static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
- fd_start(cur_drv);
- if (fdctrl->fifo[2] <= cur_drv->track)
- cur_drv->dir = 1;
- else
- cur_drv->dir = 0;
fdctrl_reset_fifo(fdctrl);
if (fdctrl->fifo[2] > cur_drv->max_track) {
fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
}
}
-static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[1] & 0x80)
cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
/* No result back */
- fdctrl_reset_fifo(fdctrl);
+ fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
{
fdctrl->config = fdctrl->fifo[2];
fdctrl->precomp_trk = fdctrl->fifo[3];
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
{
fdctrl->pwrd = fdctrl->fifo[1];
fdctrl->fifo[0] = fdctrl->fifo[1];
fdctrl_set_fifo(fdctrl, 1, 1);
}
-static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
{
/* No result back */
fdctrl_reset_fifo(fdctrl);
}
-static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv = get_cur_drv(fdctrl);
if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
/* Command parameters done */
} else if (fdctrl->data_len > 7) {
/* ERROR */
fdctrl->fifo[0] = 0x80 |
- (cur_drv->head << 2) | fdctrl->cur_drv;
+ (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
fdctrl_set_fifo(fdctrl, 1, 1);
}
}
-static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
- fd_start(cur_drv);
- cur_drv->dir = 0;
if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
cur_drv->track = cur_drv->max_track - 1;
} else {
cur_drv->track += fdctrl->fifo[2];
}
fdctrl_reset_fifo(fdctrl);
+ /* Raise Interrupt */
fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
}
-static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
+static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
{
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDrive *cur_drv;
- fdctrl->cur_drv = fdctrl->fifo[1] & FD_DOR_SELMASK;
+ SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
cur_drv = get_cur_drv(fdctrl);
- fd_start(cur_drv);
- cur_drv->dir = 1;
if (fdctrl->fifo[2] > cur_drv->track) {
cur_drv->track = 0;
} else {
uint8_t mask;
const char* name;
int parameters;
- void (*handler)(fdctrl_t *fdctrl, int direction);
+ void (*handler)(FDCtrl *fdctrl, int direction);
int direction;
} handlers[] = {
{ FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
/* Associate command to an index in the 'handlers' array */
static uint8_t command_to_handler[256];
-static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
+static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
{
- fdrive_t *cur_drv;
+ FDrive *cur_drv;
int pos;
- cur_drv = get_cur_drv(fdctrl);
/* Reset mode */
- if (fdctrl->state & FD_CTRL_RESET) {
+ if (!(fdctrl->dor & FD_DOR_nRESET)) {
FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
return;
}
- fdctrl->state &= ~FD_CTRL_SLEEP;
- if (FD_STATE(fdctrl->data_state) == FD_STATE_STATUS) {
- FLOPPY_ERROR("can't write data in status mode\n");
+ if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
+ FLOPPY_ERROR("controller not ready for writing\n");
return;
}
+ fdctrl->dsr &= ~FD_DSR_PWRDOWN;
/* Is it write command time ? */
- if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA) {
+ if (fdctrl->msr & FD_MSR_NONDMA) {
/* FIFO data write */
- fdctrl->fifo[fdctrl->data_pos++] = value;
- if (fdctrl->data_pos % FD_SECTOR_LEN == (FD_SECTOR_LEN - 1) ||
+ pos = fdctrl->data_pos++;
+ pos %= FD_SECTOR_LEN;
+ fdctrl->fifo[pos] = value;
+ if (pos == FD_SECTOR_LEN - 1 ||
fdctrl->data_pos == fdctrl->data_len) {
- bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1);
+ cur_drv = get_cur_drv(fdctrl);
+ if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
+ FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
+ return;
+ }
if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
FLOPPY_DPRINTF("error seeking to next sector %d\n",
fd_sector(cur_drv));
/* Switch from transfer mode to status mode
* then from status mode to command mode
*/
- if (FD_STATE(fdctrl->data_state) == FD_STATE_DATA)
+ if (fdctrl->data_pos == fdctrl->data_len)
fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
return;
}
}
FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
- fdctrl->fifo[fdctrl->data_pos] = value;
- if (++fdctrl->data_pos == fdctrl->data_len) {
+ fdctrl->fifo[fdctrl->data_pos++] = value;
+ if (fdctrl->data_pos == fdctrl->data_len) {
/* We now have all parameters
* and will be able to treat the command
*/
static void fdctrl_result_timer(void *opaque)
{
- fdctrl_t *fdctrl = opaque;
- fdrive_t *cur_drv = get_cur_drv(fdctrl);
+ FDCtrl *fdctrl = opaque;
+ FDrive *cur_drv = get_cur_drv(fdctrl);
/* Pretend we are spinning.
* This is needed for Coherent, which uses READ ID to check for
}
/* Init functions */
-static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
- target_phys_addr_t io_base,
- BlockDriverState **fds)
+static void fdctrl_connect_drives(FDCtrl *fdctrl)
+{
+ unsigned int i;
+
+ for (i = 0; i < MAX_FD; i++) {
+ fd_init(&fdctrl->drives[i]);
+ fd_revalidate(&fdctrl->drives[i]);
+ }
+}
+
+FDCtrl *fdctrl_init_isa(DriveInfo **fds)
+{
+ ISADevice *dev;
+
+ dev = isa_create("isa-fdc");
+ if (fds[0]) {
+ qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]);
+ }
+ if (fds[1]) {
+ qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
+ }
+ if (qdev_init(&dev->qdev) < 0)
+ return NULL;
+ return &(DO_UPCAST(FDCtrlISABus, busdev, dev)->state);
+}
+
+FDCtrl *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
+ target_phys_addr_t mmio_base, DriveInfo **fds)
+{
+ FDCtrl *fdctrl;
+ DeviceState *dev;
+ FDCtrlSysBus *sys;
+
+ dev = qdev_create(NULL, "sysbus-fdc");
+ sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
+ fdctrl = &sys->state;
+ fdctrl->dma_chann = dma_chann; /* FIXME */
+ if (fds[0]) {
+ qdev_prop_set_drive(dev, "driveA", fds[0]);
+ }
+ if (fds[1]) {
+ qdev_prop_set_drive(dev, "driveB", fds[1]);
+ }
+ qdev_init_nofail(dev);
+ sysbus_connect_irq(&sys->busdev, 0, irq);
+ sysbus_mmio_map(&sys->busdev, 0, mmio_base);
+
+ return fdctrl;
+}
+
+FDCtrl *sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
+ DriveInfo **fds, qemu_irq *fdc_tc)
+{
+ DeviceState *dev;
+ FDCtrlSysBus *sys;
+ FDCtrl *fdctrl;
+
+ dev = qdev_create(NULL, "SUNW,fdtwo");
+ if (fds[0]) {
+ qdev_prop_set_drive(dev, "drive", fds[0]);
+ }
+ qdev_init_nofail(dev);
+ sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
+ fdctrl = &sys->state;
+ sysbus_connect_irq(&sys->busdev, 0, irq);
+ sysbus_mmio_map(&sys->busdev, 0, io_base);
+ *fdc_tc = qdev_get_gpio_in(dev, 0);
+
+ return fdctrl;
+}
+
+static int fdctrl_init_common(FDCtrl *fdctrl, target_phys_addr_t io_base)
{
- fdctrl_t *fdctrl;
int i, j;
+ static int command_tables_inited = 0;
/* Fill 'command_to_handler' lookup table */
- for (i = sizeof(handlers)/sizeof(handlers[0]) - 1; i >= 0; i--) {
- for (j = 0; j < sizeof(command_to_handler); j++) {
- if ((j & handlers[i].mask) == handlers[i].value)
- command_to_handler[j] = i;
+ if (!command_tables_inited) {
+ command_tables_inited = 1;
+ for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
+ for (j = 0; j < sizeof(command_to_handler); j++) {
+ if ((j & handlers[i].mask) == handlers[i].value) {
+ command_to_handler[j] = i;
+ }
+ }
}
}
FLOPPY_DPRINTF("init controller\n");
- fdctrl = qemu_mallocz(sizeof(fdctrl_t));
- if (!fdctrl)
- return NULL;
fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
- if (fdctrl->fifo == NULL) {
- qemu_free(fdctrl);
- return NULL;
- }
+ fdctrl->fifo_size = 512;
fdctrl->result_timer = qemu_new_timer(vm_clock,
fdctrl_result_timer, fdctrl);
fdctrl->version = 0x90; /* Intel 82078 controller */
- fdctrl->irq = irq;
- fdctrl->dma_chann = dma_chann;
- fdctrl->io_base = io_base;
fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
- if (fdctrl->dma_chann != -1) {
- fdctrl->dma_en = 1;
- DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
- } else {
- fdctrl->dma_en = 0;
- }
- for (i = 0; i < MAX_FD; i++) {
- fd_init(&fdctrl->drives[i], fds[i]);
- }
- fdctrl_reset(fdctrl, 0);
- fdctrl->state = FD_CTRL_ACTIVE;
- register_savevm("fdc", io_base, 1, fdc_save, fdc_load, fdctrl);
- qemu_register_reset(fdctrl_external_reset, fdctrl);
- for (i = 0; i < MAX_FD; i++) {
- fd_revalidate(&fdctrl->drives[i]);
- }
+ fdctrl->num_floppies = MAX_FD;
- return fdctrl;
+ if (fdctrl->dma_chann != -1)
+ DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
+ fdctrl_connect_drives(fdctrl);
+
+ vmstate_register(io_base, &vmstate_fdc, fdctrl);
+ return 0;
}
-fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
- target_phys_addr_t io_base,
- BlockDriverState **fds)
+static int isabus_fdc_init1(ISADevice *dev)
{
- fdctrl_t *fdctrl;
- int io_mem;
+ FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
+ FDCtrl *fdctrl = &isa->state;
+ int iobase = 0x3f0;
+ int isairq = 6;
+ int dma_chann = 2;
+ int ret;
- fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
+ register_ioport_read(iobase + 0x01, 5, 1,
+ &fdctrl_read_port, fdctrl);
+ register_ioport_read(iobase + 0x07, 1, 1,
+ &fdctrl_read_port, fdctrl);
+ register_ioport_write(iobase + 0x01, 5, 1,
+ &fdctrl_write_port, fdctrl);
+ register_ioport_write(iobase + 0x07, 1, 1,
+ &fdctrl_write_port, fdctrl);
+ isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
+ fdctrl->dma_chann = dma_chann;
- fdctrl->sun4m = 0;
- if (mem_mapped) {
- io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
- fdctrl);
- cpu_register_physical_memory(io_base, 0x08, io_mem);
- } else {
- register_ioport_read((uint32_t)io_base + 0x01, 5, 1, &fdctrl_read,
- fdctrl);
- register_ioport_read((uint32_t)io_base + 0x07, 1, 1, &fdctrl_read,
- fdctrl);
- register_ioport_write((uint32_t)io_base + 0x01, 5, 1, &fdctrl_write,
- fdctrl);
- register_ioport_write((uint32_t)io_base + 0x07, 1, 1, &fdctrl_write,
- fdctrl);
- }
+ ret = fdctrl_init_common(fdctrl, iobase);
- return fdctrl;
+ return ret;
}
-fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
- BlockDriverState **fds, qemu_irq *fdc_tc)
+static int sysbus_fdc_init1(SysBusDevice *dev)
{
- fdctrl_t *fdctrl;
- int io_mem;
+ FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
+ FDCtrl *fdctrl = &sys->state;
+ int io;
+ int ret;
+
+ io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
+ sysbus_init_mmio(dev, 0x08, io);
+ sysbus_init_irq(dev, &fdctrl->irq);
+ qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
+ fdctrl->dma_chann = -1;
+
+ ret = fdctrl_init_common(fdctrl, io);
+
+ return ret;
+}
+
+static int sun4m_fdc_init1(SysBusDevice *dev)
+{
+ FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
+ int io;
+
+ io = cpu_register_io_memory(fdctrl_mem_read_strict,
+ fdctrl_mem_write_strict, fdctrl);
+ sysbus_init_mmio(dev, 0x08, io);
+ sysbus_init_irq(dev, &fdctrl->irq);
+ qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
- fdctrl = fdctrl_init_common(irq, 0, io_base, fds);
fdctrl->sun4m = 1;
- io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
- fdctrl_mem_write_strict,
- fdctrl);
- cpu_register_physical_memory(io_base, 0x08, io_mem);
- *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
+ return fdctrl_init_common(fdctrl, io);
+}
+
+static ISADeviceInfo isa_fdc_info = {
+ .init = isabus_fdc_init1,
+ .qdev.name = "isa-fdc",
+ .qdev.size = sizeof(FDCtrlISABus),
+ .qdev.no_user = 1,
+ .qdev.reset = fdctrl_external_reset_isa,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].dinfo),
+ DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].dinfo),
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
- return fdctrl;
+static SysBusDeviceInfo sysbus_fdc_info = {
+ .init = sysbus_fdc_init1,
+ .qdev.name = "sysbus-fdc",
+ .qdev.size = sizeof(FDCtrlSysBus),
+ .qdev.reset = fdctrl_external_reset_sysbus,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].dinfo),
+ DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].dinfo),
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+static SysBusDeviceInfo sun4m_fdc_info = {
+ .init = sun4m_fdc_init1,
+ .qdev.name = "SUNW,fdtwo",
+ .qdev.size = sizeof(FDCtrlSysBus),
+ .qdev.reset = fdctrl_external_reset_sysbus,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].dinfo),
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+static void fdc_register_devices(void)
+{
+ isa_qdev_register(&isa_fdc_info);
+ sysbus_register_withprop(&sysbus_fdc_info);
+ sysbus_register_withprop(&sun4m_fdc_info);
}
+
+device_init(fdc_register_devices)
projects / mirror_qemu.git / blobdiff