#include "sysbus.h"
#include "hw.h"
-#include "net.h"
+#include "net/net.h"
#include "flash.h"
#include "sysemu.h"
#include "devices.h"
#include "boards.h"
#include "xilinx.h"
#include "blockdev.h"
-#include "exec-memory.h"
+#include "exec/address-spaces.h"
#include "microblaze_boot.h"
#include "microblaze_pic_cpu.h"
#define UARTLITE_BASEADDR 0x84000000
#define ETHLITE_BASEADDR 0x81000000
-static void machine_cpu_reset(CPUMBState *env)
+static void machine_cpu_reset(MicroBlazeCPU *cpu)
{
+ CPUMBState *env = &cpu->env;
+
env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
}
static void
-petalogix_s3adsp1800_init(ram_addr_t ram_size,
- const char *boot_device,
- const char *kernel_filename,
- const char *kernel_cmdline,
- const char *initrd_filename, const char *cpu_model)
+petalogix_s3adsp1800_init(QEMUMachineInitArgs *args)
{
+ ram_addr_t ram_size = args->ram_size;
+ const char *cpu_model = args->cpu_model;
DeviceState *dev;
+ MicroBlazeCPU *cpu;
CPUMBState *env;
DriveInfo *dinfo;
int i;
- target_phys_addr_t ddr_base = MEMORY_BASEADDR;
+ hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
if (cpu_model == NULL) {
cpu_model = "microblaze";
}
- env = cpu_init(cpu_model);
+ cpu = cpu_mb_init(cpu_model);
+ env = &cpu->env;
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram,
irq[i] = qdev_get_gpio_in(dev, i);
}
- sysbus_create_simple("xilinx,uartlite", UARTLITE_BASEADDR, irq[3]);
+ sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]);
/* 2 timers at irq 2 @ 62 Mhz. */
- xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
+ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000);
xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);
- microblaze_load_kernel(env, ddr_base, ram_size,
+ microblaze_load_kernel(cpu, ddr_base, ram_size,
BINARY_DEVICE_TREE_FILE, machine_cpu_reset);
}