* THE SOFTWARE.
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "mac.h"
#include "hw/input/adb.h"
-#include "hw/timer/m48t59.h"
#include "sysemu/sysemu.h"
#include "net/net.h"
#include "hw/isa/isa.h"
#include "hw/pci/pci.h"
+#include "hw/pci/pci_host.h"
#include "hw/boards.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/char/escc.h"
+#include "hw/misc/macio/macio.h"
#include "hw/ide.h"
#include "hw/loader.h"
+#include "hw/fw-path-provider.h"
#include "elf.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
-#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"
-#include "qemu/cutils.h"
#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510
#define NDRV_VGA_FILENAME "qemu_vga.ndrv"
+#define GRACKLE_BASE 0xfec00000
+
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
Error **errp)
{
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static hwaddr round_page(hwaddr addr)
-{
- return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
-}
-
static void ppc_heathrow_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
- qemu_irq *pic, **heathrow_irqs;
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
- MemoryRegion *isa = g_new(MemoryRegion, 1);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
- PCIDevice *macio;
+ OldWorldMacIOState *macio;
MACIOIDEState *macio_ide;
- DeviceState *dev;
+ SysBusDevice *s;
+ DeviceState *dev, *pic_dev;
BusState *adb_bus;
- int bios_size, ndrv_size;
- uint8_t *ndrv_file;
- MemoryRegion *pic_mem;
- MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1);
+ int bios_size;
uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
- if (machine->cpu_model == NULL)
- machine->cpu_model = "G3";
for (i = 0; i < smp_cpus; i++) {
- cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU,
- machine->cpu_model));
- if (cpu == NULL) {
- fprintf(stderr, "Unable to find PowerPC CPU definition\n");
- exit(1);
- }
+ cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
/* Set time-base frequency to 16.6 Mhz */
}
/* allocate RAM */
- if (ram_size > (2047 << 20)) {
- fprintf(stderr,
- "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
- ((unsigned int)ram_size / (1 << 20)));
+ if (ram_size > 2047 * MiB) {
+ error_report("Too much memory for this machine: %" PRId64 " MB, "
+ "maximum 2047 MB", ram_size / MiB);
exit(1);
}
/* Load OpenBIOS (ELF) */
if (filename) {
- bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
+ bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL,
1, PPC_ELF_MACHINE, 0, 0);
g_free(filename);
} else {
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
- kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
+ kernel_size = load_elf(kernel_filename, NULL,
+ translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
0, 0);
if (kernel_size < 0)
}
/* load initrd */
if (initrd_filename) {
- initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
+ initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
initrd_filename);
exit(1);
}
- cmdline_base = round_page(initrd_base + initrd_size);
+ cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
} else {
initrd_base = 0;
initrd_size = 0;
- cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
+ cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
}
ppc_boot_device = 'm';
} else {
#endif
}
if (ppc_boot_device == '\0') {
- fprintf(stderr, "No valid boot device for G3 Beige machine\n");
+ error_report("No valid boot device for G3 Beige machine");
exit(1);
}
}
- /* Register 2 MB of ISA IO space */
- memory_region_init_alias(isa, NULL, "isa_mmio",
- get_system_io(), 0, 0x00200000);
- memory_region_add_subregion(sysmem, 0xfe000000, isa);
-
/* XXX: we register only 1 output pin for heathrow PIC */
- heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
- heathrow_irqs[0] =
- g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
+ pic_dev = qdev_create(NULL, TYPE_HEATHROW);
+ qdev_init_nofail(pic_dev);
+
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
- heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
- heathrow_irqs[i][0] =
- ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
+ qdev_connect_gpio_out(pic_dev, 0,
+ ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
break;
default:
error_report("Bus model not supported on OldWorld Mac machine");
error_report("Only 6xx bus is supported on heathrow machine");
exit(1);
}
- pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
- pci_bus = pci_grackle_init(0xfec00000, pic,
- get_system_memory(),
- get_system_io());
- pci_vga_init(pci_bus);
- escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
- serial_hds[1], ESCC_CLOCK, 4);
- memory_region_init_alias(escc_bar, NULL, "escc-bar",
- escc_mem, 0, memory_region_size(escc_mem));
+ /* Grackle PCI host bridge */
+ dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
+ qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
+ object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
+ &error_abort);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(s, 0, GRACKLE_BASE);
+ sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
+ /* PCI hole */
+ memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
+ sysbus_mmio_get_region(s, 2));
+ /* Register 2 MB of ISA IO space */
+ memory_region_add_subregion(get_system_memory(), 0xfe000000,
+ sysbus_mmio_get_region(s, 3));
- for(i = 0; i < nb_nics; i++)
- pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
+ pci_bus = PCI_HOST_BRIDGE(dev)->bus;
+
+ pci_vga_init(pci_bus);
+ for (i = 0; i < nb_nics; i++) {
+ pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
+ }
ide_drive_get(hd, ARRAY_SIZE(hd));
- macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
+ /* MacIO */
+ macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO));
dev = DEVICE(macio);
- qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
- qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
- qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
- qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
- qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
qdev_prop_set_uint64(dev, "frequency", tbfreq);
- macio_init(macio, pic_mem, escc_bar);
+ object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
+ &error_abort);
+ qdev_init_nofail(dev);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
/* No PCI init: the BIOS will do it */
- fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
+ dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
+ fw_cfg = FW_CFG(dev);
+ qdev_prop_set_uint32(dev, "data_width", 1);
+ qdev_prop_set_bit(dev, "dma_enabled", false);
+ object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
+ OBJECT(fw_cfg), NULL);
+ qdev_init_nofail(dev);
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_mmio_map(s, 0, CFG_ADDR);
+ sysbus_mmio_map(s, 1, CFG_ADDR + 2);
+
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
/* MacOS NDRV VGA driver */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
if (filename) {
- ndrv_size = get_image_size(filename);
- if (ndrv_size != -1) {
- ndrv_file = g_malloc(ndrv_size);
- ndrv_size = load_image(filename, ndrv_file);
+ gchar *ndrv_file;
+ gsize ndrv_size;
+ if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
}
g_free(filename);
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
+/*
+ * Implementation of an interface to adjust firmware path
+ * for the bootindex property handling.
+ */
+static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
+ DeviceState *dev)
+{
+ PCIDevice *pci;
+ IDEBus *ide_bus;
+ IDEState *ide_s;
+ MACIOIDEState *macio_ide;
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
+ pci = PCI_DEVICE(dev);
+ return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
+ macio_ide = MACIO_IDE(dev);
+ return g_strdup_printf("ata-3@%x", macio_ide->addr);
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) {
+ ide_bus = IDE_BUS(qdev_get_parent_bus(dev));
+ ide_s = idebus_active_if(ide_bus);
+
+ if (ide_s->drive_kind == IDE_CD) {
+ return g_strdup("cdrom");
+ }
+
+ return g_strdup("hd");
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
+ return g_strdup("hd");
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
+ return g_strdup("cdrom");
+ }
+
+ if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
+ return g_strdup("disk");
+ }
+
+ return NULL;
+}
+
static int heathrow_kvm_type(const char *arg)
{
/* Always force PR KVM */
return 2;
}
-static void heathrow_machine_init(MachineClass *mc)
+static void heathrow_class_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
+
mc->desc = "Heathrow based PowerMAC";
mc->init = ppc_heathrow_init;
mc->block_default_type = IF_IDE;
/* TOFIX "cad" when Mac floppy is implemented */
mc->default_boot_order = "cd";
mc->kvm_type = heathrow_kvm_type;
+ mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
+ mc->default_display = "std";
+ mc->ignore_boot_device_suffixes = true;
+ fwc->get_dev_path = heathrow_fw_dev_path;
+}
+
+static const TypeInfo ppc_heathrow_machine_info = {
+ .name = MACHINE_TYPE_NAME("g3beige"),
+ .parent = TYPE_MACHINE,
+ .class_init = heathrow_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_FW_PATH_PROVIDER },
+ { }
+ },
+};
+
+static void ppc_heathrow_register_types(void)
+{
+ type_register_static(&ppc_heathrow_machine_info);
}
-DEFINE_MACHINE("g3beige", heathrow_machine_init)
+type_init(ppc_heathrow_register_types);
projects / mirror_qemu.git / blobdiff