};
struct PPCE500PCIState {
- PCIHostState pci_state;
struct pci_outbound pob[PPCE500_PCI_NR_POBS];
struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
uint32_t gasket_time;
- uint64_t base_addr;
+ PCIHostState pci_state;
+ PCIDevice *pci_dev;
};
typedef struct PPCE500PCIState PPCE500PCIState;
ret = (irq_num + devno - 0x10) % 4;
break;
default:
- printf("Error:%s:unknow dev number\n", __func__);
+ printf("Error:%s:unknown dev number\n", __func__);
}
pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__,
qemu_set_irq(pic[irq_num], level);
}
-static void ppce500_pci_save(QEMUFile *f, void *opaque)
-{
- PPCE500PCIState *controller = opaque;
- int i;
-
- /* pci_device_save(controller->pci_dev, f); */
-
- for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
- qemu_put_be32s(f, &controller->pob[i].potar);
- qemu_put_be32s(f, &controller->pob[i].potear);
- qemu_put_be32s(f, &controller->pob[i].powbar);
- qemu_put_be32s(f, &controller->pob[i].powar);
+static const VMStateDescription vmstate_pci_outbound = {
+ .name = "pci_outbound",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(potar, struct pci_outbound),
+ VMSTATE_UINT32(potear, struct pci_outbound),
+ VMSTATE_UINT32(powbar, struct pci_outbound),
+ VMSTATE_UINT32(powar, struct pci_outbound),
+ VMSTATE_END_OF_LIST()
}
+};
- for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
- qemu_put_be32s(f, &controller->pib[i].pitar);
- qemu_put_be32s(f, &controller->pib[i].piwbar);
- qemu_put_be32s(f, &controller->pib[i].piwbear);
- qemu_put_be32s(f, &controller->pib[i].piwar);
- }
- qemu_put_be32s(f, &controller->gasket_time);
-}
-
-static int ppce500_pci_load(QEMUFile *f, void *opaque, int version_id)
-{
- PPCE500PCIState *controller = opaque;
- int i;
-
- if (version_id != 1)
- return -EINVAL;
-
- /* pci_device_load(controller->pci_dev, f); */
-
- for (i = 0; i < PPCE500_PCI_NR_POBS; i++) {
- qemu_get_be32s(f, &controller->pob[i].potar);
- qemu_get_be32s(f, &controller->pob[i].potear);
- qemu_get_be32s(f, &controller->pob[i].powbar);
- qemu_get_be32s(f, &controller->pob[i].powar);
+static const VMStateDescription vmstate_pci_inbound = {
+ .name = "pci_inbound",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(pitar, struct pci_inbound),
+ VMSTATE_UINT32(piwbar, struct pci_inbound),
+ VMSTATE_UINT32(piwbear, struct pci_inbound),
+ VMSTATE_UINT32(piwar, struct pci_inbound),
+ VMSTATE_END_OF_LIST()
}
+};
- for (i = 0; i < PPCE500_PCI_NR_PIBS; i++) {
- qemu_get_be32s(f, &controller->pib[i].pitar);
- qemu_get_be32s(f, &controller->pib[i].piwbar);
- qemu_get_be32s(f, &controller->pib[i].piwbear);
- qemu_get_be32s(f, &controller->pib[i].piwar);
+static const VMStateDescription vmstate_ppce500_pci = {
+ .name = "ppce500_pci",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE_POINTER(pci_dev, PPCE500PCIState),
+ VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
+ vmstate_pci_outbound, struct pci_outbound),
+ VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
+ vmstate_pci_outbound, struct pci_inbound),
+ VMSTATE_UINT32(gasket_time, PPCE500PCIState),
+ VMSTATE_END_OF_LIST()
}
- qemu_get_be32s(f, &controller->gasket_time);
-
- return 0;
-}
+};
PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers)
{
- DeviceState *dev;
- PCIBus *b;
- PCIHostState *h;
- PPCE500PCIState *s;
+ PPCE500PCIState *controller;
PCIDevice *d;
+ int index;
static int ppce500_pci_id;
- dev = qdev_create(NULL, "e500-pcihost");
- h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
- s = DO_UPCAST(PPCE500PCIState, pci_state, h);
+ controller = qemu_mallocz(sizeof(PPCE500PCIState));
- qdev_prop_set_uint64(dev, "base_addr", registers);
- b = pci_register_bus(&s->pci_state.busdev.qdev, NULL, mpc85xx_pci_set_irq,
- mpc85xx_pci_map_irq, pci_irqs, PCI_DEVFN(0x11, 0), 4);
+ controller->pci_state.bus = pci_register_bus(NULL, "pci",
+ mpc85xx_pci_set_irq,
+ mpc85xx_pci_map_irq,
+ pci_irqs, PCI_DEVFN(0x11, 0),
+ 4);
+ d = pci_register_device(controller->pci_state.bus,
+ "host bridge", sizeof(PCIDevice),
+ 0, NULL, NULL);
- s->pci_state.bus = b;
- qdev_init_nofail(dev);
- d = pci_create_simple(b, 0, "e500-host-bridge");
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_FREESCALE);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_MPC8533E);
+ pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_POWERPC);
- /* XXX load/save code not tested. */
- register_savevm(&d->qdev, "ppce500_pci", ppce500_pci_id++,
- 1, ppce500_pci_save, ppce500_pci_load, s);
-
- return b;
-}
-
-static int e500_pcihost_initfn(SysBusDevice *dev)
-{
- PCIHostState *h;
- PPCE500PCIState *s;
- target_phys_addr_t registers;
- int index;
-
- h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
- s = DO_UPCAST(PPCE500PCIState, pci_state, h);
- registers = (target_phys_addr_t)s->base_addr;
+ controller->pci_dev = d;
/* CFGADDR */
- index = pci_host_conf_register_mmio(&s->pci_state, 0);
+ index = pci_host_conf_register_mmio(&controller->pci_state,
+ DEVICE_BIG_ENDIAN);
if (index < 0)
- return -1;
+ goto free;
cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index);
/* CFGDATA */
- index = pci_host_data_register_mmio(&s->pci_state, 1);
+ index = pci_host_data_register_mmio(&controller->pci_state,
+ DEVICE_BIG_ENDIAN);
if (index < 0)
- return -1;
+ goto free;
cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index);
index = cpu_register_io_memory(e500_pci_reg_read,
- e500_pci_reg_write, s);
+ e500_pci_reg_write, controller,
+ DEVICE_NATIVE_ENDIAN);
if (index < 0)
- return -1;
+ goto free;
cpu_register_physical_memory(registers + PCIE500_REG_BASE,
PCIE500_REG_SIZE, index);
- return 0;
-}
-static int e500_host_bridge_initfn(PCIDevice *dev)
-{
- pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_FREESCALE);
- pci_config_set_device_id(dev->config, PCI_DEVICE_ID_MPC8533E);
- pci_config_set_class(dev->config, PCI_CLASS_PROCESSOR_POWERPC);
-
- return 0;
-}
-
-static PCIDeviceInfo e500_host_bridge_info = {
- .qdev.name = "e500-host-bridge",
- .qdev.desc = "Host bridge",
- .qdev.size = sizeof(PCIDevice),
- .qdev.no_user = 1,
- .init = e500_host_bridge_initfn,
-};
+ /* XXX load/save code not tested. */
+ vmstate_register(&d->qdev, ppce500_pci_id++, &vmstate_ppce500_pci,
+ controller);
-static SysBusDeviceInfo e500_pcihost_info = {
- .init = e500_pcihost_initfn,
- .qdev.name = "e500-pcihost",
- .qdev.size = sizeof(PPCE500PCIState),
- .qdev.no_user = 1,
- .qdev.props = (Property[]) {
- DEFINE_PROP_UINT64("base_addr", PPCE500PCIState, base_addr, 0),
- DEFINE_PROP_END_OF_LIST(),
- }
-};
+ return controller->pci_state.bus;
-static void e500_pci_register(void)
-{
- sysbus_register_withprop(&e500_pcihost_info);
- pci_qdev_register(&e500_host_bridge_info);
+free:
+ printf("%s error\n", __func__);
+ qemu_free(controller);
+ return NULL;
}
-device_init(e500_pci_register);
projects / qemu.git / blobdiff