ehci: fix port count.

[qemu.git] / hw / tusb6010.c

diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index f3aa7b1f807e8059bf7bcf477052daafc0a15a53..ccd01ad4437b5c351504134c17dfd7430ef4de8d 100644 (file)
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -16,8 +16,7 @@
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "qemu-common.h"
 #include "qemu-timer.h"
@@ -287,8 +286,8 @@ static void tusb_gpio_intr_update(TUSBState *s)
     /* TODO: How is this signalled?  */
 }
 
-extern CPUReadMemoryFunc *musb_read[];
-extern CPUWriteMemoryFunc *musb_write[];
+extern CPUReadMemoryFunc * const musb_read[];
+extern CPUWriteMemoryFunc * const musb_write[];
 
 static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
 {
@@ -426,7 +425,6 @@ static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
         return s->rx_config[epnum];
     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
-        epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
         return 0x00000000;     /* TODO */
     case TUSB_WAIT_COUNT:
         return 0x00;           /* TODO */
@@ -522,9 +520,9 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
     case TUSB_DEV_OTG_TIMER:
         s->otg_timer_val = value;
         if (value & TUSB_DEV_OTG_TIMER_ENABLE)
-            qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) +
+            qemu_mod_timer(s->otg_timer, qemu_get_clock_ns(vm_clock) +
                             muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
-                                    ticks_per_sec, TUSB_DEVCLOCK));
+                                     get_ticks_per_sec(), TUSB_DEVCLOCK));
         else
             qemu_del_timer(s->otg_timer);
         break;
@@ -631,7 +629,6 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
         break;
     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
-        epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
         return;                /* TODO */
     case TUSB_WAIT_COUNT:
         return;                /* TODO */
@@ -650,13 +647,13 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *tusb_async_readfn[] = {
+static CPUReadMemoryFunc * const tusb_async_readfn[] = {
     tusb_async_readb,
     tusb_async_readh,
     tusb_async_readw,
 };
 
-static CPUWriteMemoryFunc *tusb_async_writefn[] = {
+static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
     tusb_async_writeb,
     tusb_async_writeh,
     tusb_async_writew,
@@ -742,11 +739,11 @@ TUSBState *tusb6010_init(qemu_irq intr)
     s->mask = 0xffffffff;
     s->intr = 0x00000000;
     s->otg_timer_val = 0;
-    s->iomemtype[1] = cpu_register_io_memory(0, tusb_async_readfn,
-                    tusb_async_writefn, s);
+    s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
+                    tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
     s->irq = intr;
-    s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s);
-    s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s);
+    s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
+    s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
     s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s,
                             __musb_irq_max));
 
@@ -764,6 +761,6 @@ void tusb6010_power(TUSBState *s, int on)
         s->intr_ok = 0;
         tusb_intr_update(s);
         qemu_mod_timer(s->pwr_timer,
-                        qemu_get_clock(vm_clock) + ticks_per_sec / 2);
+                       qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 2);
     }
 }