*/
#include "sysbus.h"
-#include "sysemu.h"
#include "qemu-timer.h"
#define D(x)
struct xlx_timer *timers;
};
-static inline unsigned int timer_from_addr(a_target_phys_addr addr)
+static inline unsigned int timer_from_addr(target_phys_addr_t addr)
{
/* Timers get a 4x32bit control reg area each. */
return addr >> 2;
qemu_set_irq(t->irq, !!irq);
}
-static uint32_t timer_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
}
static void
-timer_writel (void *opaque, a_target_phys_addr addr, uint32_t value)
+timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
ptimer_set_freq(xt->ptimer, t->freq_hz);
}
- timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
+ timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
return 0;
}