#ifndef ALPHA_CPU_H
#define ALPHA_CPU_H
-#include "qemu-common.h"
#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
-#define TARGET_LONG_BITS 64
#define ALIGNED_ONLY
-#define CPUArchState struct CPUAlphaState
-
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
-#include "exec/cpu-defs.h"
-
#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32
-#define TARGET_PAGE_BITS 13
-
-#ifdef CONFIG_USER_ONLY
-/* ??? The kernel likes to give addresses in high memory. If the host has
- more virtual address space than the guest, this can lead to impossible
- allocations. Honor the long-standing assumption that only kernel addrs
- are negative, but otherwise allow allocations anywhere. This could lead
- to tricky emulation problems for programs doing tagged addressing, but
- that's far fewer than encounter the impossible allocation problem. */
-#define TARGET_PHYS_ADDR_SPACE_BITS 63
-#define TARGET_VIRT_ADDR_SPACE_BITS 63
-#else
-/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
-#define TARGET_PHYS_ADDR_SPACE_BITS 44
-#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
-#endif
-
/* Alpha major type */
enum {
ALPHA_EV3 = 1,
#define SWCR_STATUS_DNO (1U << 22)
#define SWCR_STATUS_MASK ((1U << 23) - (1U << 17))
+#define SWCR_STATUS_TO_EXCSUM_SHIFT 16
+
#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
/* MMU modes definitions */
PALcode cheats and usees the KSEG mapping for its code+data rather than
physical addresses. */
-#define NB_MMU_MODES 3
-
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX 0
/* The FPCR, and disassembled portions thereof. */
uint32_t fpcr;
+#ifdef CONFIG_USER_ONLY
+ uint32_t swcr;
+#endif
uint32_t fpcr_exc_enable;
float_status fp_status;
uint8_t fpcr_dyn_round;
/* This alarm doesn't exist in real hardware; we wish it did. */
uint64_t alarm_expire;
- /* Those resources are used only in QEMU core */
- CPU_COMMON
-
int error_code;
uint32_t features;
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUAlphaState env;
/* This alarm doesn't exist in real hardware; we wish it did. */
QEMUTimer *alarm_timer;
};
-static inline AlphaCPU *alpha_env_get_cpu(CPUAlphaState *env)
-{
- return container_of(env, AlphaCPU, env);
-}
-
-#define ENV_GET_CPU(e) CPU(alpha_env_get_cpu(e))
-
-#define ENV_OFFSET offsetof(AlphaCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_alpha_cpu;
#define cpu_list alpha_cpu_list
#define cpu_signal_handler cpu_alpha_signal_handler
+typedef CPUAlphaState CPUArchState;
+typedef AlphaCPU ArchCPU;
+
#include "exec/cpu-all.h"
enum {
*pflags = env->flags & ENV_FLAG_TB_MASK;
}
+#ifdef CONFIG_USER_ONLY
+/* Copied from linux ieee_swcr_to_fpcr. */
+static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
+{
+ uint64_t fpcr = 0;
+
+ fpcr |= (swcr & SWCR_STATUS_MASK) << 35;
+ fpcr |= (swcr & SWCR_MAP_DMZ) << 36;
+ fpcr |= (~swcr & (SWCR_TRAP_ENABLE_INV
+ | SWCR_TRAP_ENABLE_DZE
+ | SWCR_TRAP_ENABLE_OVF)) << 48;
+ fpcr |= (~swcr & (SWCR_TRAP_ENABLE_UNF
+ | SWCR_TRAP_ENABLE_INE)) << 57;
+ fpcr |= (swcr & SWCR_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
+ fpcr |= (~swcr & SWCR_TRAP_ENABLE_DNO) << 41;
+
+ return fpcr;
+}
+
+/* Copied from linux ieee_fpcr_to_swcr. */
+static inline uint64_t alpha_ieee_fpcr_to_swcr(uint64_t fpcr)
+{
+ uint64_t swcr = 0;
+
+ swcr |= (fpcr >> 35) & SWCR_STATUS_MASK;
+ swcr |= (fpcr >> 36) & SWCR_MAP_DMZ;
+ swcr |= (~fpcr >> 48) & (SWCR_TRAP_ENABLE_INV
+ | SWCR_TRAP_ENABLE_DZE
+ | SWCR_TRAP_ENABLE_OVF);
+ swcr |= (~fpcr >> 57) & (SWCR_TRAP_ENABLE_UNF | SWCR_TRAP_ENABLE_INE);
+ swcr |= (fpcr >> 47) & SWCR_MAP_UMZ;
+ swcr |= (~fpcr >> 41) & SWCR_TRAP_ENABLE_DNO;
+
+ return swcr;
+}
+#endif /* CONFIG_USER_ONLY */
+
#endif /* ALPHA_CPU_H */