env->pregs[PR_ERP] = env->pc;
}
+void crisv10_cpu_do_interrupt(CPUState *cs)
+{
+ cris_cpu_do_interrupt(cs);
+}
+
int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
int mmu_idx)
{
+ CRISCPU *cpu = cris_env_get_cpu(env);
+
env->exception_index = 0xaa;
env->pregs[PR_EDA] = address;
- cpu_dump_state(env, stderr, fprintf, 0);
+ cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
return 1;
}
return r;
}
-static void do_interruptv10(CPUCRISState *env)
+void crisv10_cpu_do_interrupt(CPUState *cs)
{
- D(CPUState *cs = CPU(cris_env_get_cpu(env)));
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
CPUCRISState *env = &cpu->env;
int ex_vec = -1;
- if (env->pregs[PR_VR] < 32) {
- return do_interruptv10(env);
- }
-
D_LOG("exception index=%d interrupt_req=%d\n",
env->exception_index,
cs->interrupt_request);