/*
* FIXME:
- * The condition code translation is in desperate need of attention. It's slow
- * and for system simulation it seems buggy. It sucks.
+ * The condition code translation is in need of attention.
*/
#include <stdarg.h>
#include "crisv32-decode.h"
#include "qemu-common.h"
-#define CRIS_STATS 0
-#if CRIS_STATS
-#define STATS(x) x
-#else
-#define STATS(x)
-#endif
-
#define DISAS_CRIS 0
#if DISAS_CRIS
#define DIS(x) x
TCGv cpu_T[2];
TCGv cpu_R[16];
TCGv cpu_PR[16];
+TCGv cc_x;
TCGv cc_src;
TCGv cc_dest;
TCGv cc_result;
int cc_op;
int cc_size;
uint32_t cc_mask;
- int flags_live; /* Wether or not $ccs is uptodate. */
- int flagx_live; /* Wether or not flags_x has the x flag known at
- translation time. */
+
+ int cc_size_uptodate; /* -1 invalid or last written value. */
+
+ int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
+ int flags_uptodate; /* Wether or not $ccs is uptodate. */
+ int flagx_known; /* Wether or not flags_x has the x flag known at
+ translation time. */
int flags_x;
- int clear_x; /* Clear x after this insn? */
+ int clear_x; /* Clear x after this insn? */
int user; /* user or kernel mode. */
int is_jmp;
- int dyn_jmp;
- uint32_t delayed_pc;
int delayed_branch;
- int bcc;
- uint32_t condlabel;
struct TranslationBlock *tb;
int singlestep_enabled;
} DisasContext;
-void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
static void gen_BUG(DisasContext *dc, char *file, int line)
{
printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
- cpu_dump_state (dc->env, stdout, fprintf, 0);
- fflush(NULL);
- cris_prepare_jmp (dc, 0x70000000 + line);
+ cpu_abort(dc->env, "%s:%d\n", file, line);
}
const char *regnames[] =
else
tcg_gen_mov_tl(tn, cpu_PR[r]);
}
-static inline void t_gen_mov_preg_TN(int r, TCGv tn)
+static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
{
if (r < 0 || r > 15)
fprintf(stderr, "wrong register write $p%d\n", r);
else if (r == PR_SRS)
tcg_gen_andi_tl(cpu_PR[r], tn, 3);
else {
- if (r == PR_PID) {
- tcg_gen_helper_0_0(helper_tlb_flush);
- }
tcg_gen_mov_tl(cpu_PR[r], tn);
+ if (r == PR_PID)
+ tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
}
}
-static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)
+static inline void t_gen_raise_exception(uint32_t index)
{
- tcg_gen_movi_tl(tn, val);
+ tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
}
static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
l1 = gen_new_label();
/* Speculative shift. */
tcg_gen_shl_tl(d, a, b);
- tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
+ tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
/* Clear dst if shift operands were to large. */
tcg_gen_movi_tl(d, 0);
gen_set_label(l1);
l1 = gen_new_label();
/* Speculative shift. */
tcg_gen_shr_tl(d, a, b);
- tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
+ tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
/* Clear dst if shift operands were to large. */
tcg_gen_movi_tl(d, 0);
gen_set_label(l1);
l1 = gen_new_label();
/* Speculative shift. */
tcg_gen_sar_tl(d, a, b);
- tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
+ tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
/* Clear dst if shift operands were to large. */
tcg_gen_sar_tl(d, a, tcg_const_tl(30));
gen_set_label(l1);
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_trunc_i64_i32(d2, t0);
- tcg_gen_discard_i64(t0);
- tcg_gen_discard_i64(t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
}
/* 64-bit unsigned muls, lower result in d and upper in d2. */
tcg_gen_shri_i64(t0, t0, 32);
tcg_gen_trunc_i64_i32(d2, t0);
- tcg_gen_discard_i64(t0);
- tcg_gen_discard_i64(t1);
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+}
+
+/* 32bit branch-free binary search for counting leading zeros. */
+static void t_gen_lz_i32(TCGv d, TCGv x)
+{
+ TCGv y, m, n;
+
+ y = tcg_temp_new(TCG_TYPE_I32);
+ m = tcg_temp_new(TCG_TYPE_I32);
+ n = tcg_temp_new(TCG_TYPE_I32);
+
+ /* y = -(x >> 16) */
+ tcg_gen_shri_i32(y, x, 16);
+ tcg_gen_neg_i32(y, y);
+
+ /* m = (y >> 16) & 16 */
+ tcg_gen_sari_i32(m, y, 16);
+ tcg_gen_andi_i32(m, m, 16);
+
+ /* n = 16 - m */
+ tcg_gen_sub_i32(n, tcg_const_i32(16), m);
+ /* x = x >> m */
+ tcg_gen_shr_i32(x, x, m);
+
+ /* y = x - 0x100 */
+ tcg_gen_subi_i32(y, x, 0x100);
+ /* m = (y >> 16) & 8 */
+ tcg_gen_sari_i32(m, y, 16);
+ tcg_gen_andi_i32(m, m, 8);
+ /* n = n + m */
+ tcg_gen_add_i32(n, n, m);
+ /* x = x << m */
+ tcg_gen_shl_i32(x, x, m);
+
+ /* y = x - 0x1000 */
+ tcg_gen_subi_i32(y, x, 0x1000);
+ /* m = (y >> 16) & 4 */
+ tcg_gen_sari_i32(m, y, 16);
+ tcg_gen_andi_i32(m, m, 4);
+ /* n = n + m */
+ tcg_gen_add_i32(n, n, m);
+ /* x = x << m */
+ tcg_gen_shl_i32(x, x, m);
+
+ /* y = x - 0x4000 */
+ tcg_gen_subi_i32(y, x, 0x4000);
+ /* m = (y >> 16) & 2 */
+ tcg_gen_sari_i32(m, y, 16);
+ tcg_gen_andi_i32(m, m, 2);
+ /* n = n + m */
+ tcg_gen_add_i32(n, n, m);
+ /* x = x << m */
+ tcg_gen_shl_i32(x, x, m);
+
+ /* y = x >> 14 */
+ tcg_gen_shri_i32(y, x, 14);
+ /* m = y & ~(y >> 1) */
+ tcg_gen_sari_i32(m, y, 1);
+ tcg_gen_not_i32(m, m);
+ tcg_gen_and_i32(m, m, y);
+
+ /* d = n + 2 - m */
+ tcg_gen_addi_i32(d, n, 2);
+ tcg_gen_sub_i32(d, d, m);
+
+ tcg_temp_free(y);
+ tcg_temp_free(m);
+ tcg_temp_free(n);
+}
+
+static void t_gen_btst(TCGv d, TCGv a, TCGv b)
+{
+ TCGv sbit;
+ TCGv bset;
+ TCGv t0;
+ int l1;
+
+ /* des ref:
+ The N flag is set according to the selected bit in the dest reg.
+ The Z flag is set if the selected bit and all bits to the right are
+ zero.
+ The X flag is cleared.
+ Other flags are left untouched.
+ The destination reg is not affected.
+
+ unsigned int fz, sbit, bset, mask, masked_t0;
+
+ sbit = T1 & 31;
+ bset = !!(T0 & (1 << sbit));
+ mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
+ masked_t0 = T0 & mask;
+ fz = !(masked_t0 | bset);
+
+ // Clear the X, N and Z flags.
+ T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
+ // Set the N and Z flags accordingly.
+ T0 |= (bset << 3) | (fz << 2);
+ */
+
+ l1 = gen_new_label();
+ sbit = tcg_temp_new(TCG_TYPE_TL);
+ bset = tcg_temp_new(TCG_TYPE_TL);
+ t0 = tcg_temp_new(TCG_TYPE_TL);
+
+ /* Compute bset and sbit. */
+ tcg_gen_andi_tl(sbit, b, 31);
+ tcg_gen_shl_tl(t0, tcg_const_tl(1), sbit);
+ tcg_gen_and_tl(bset, a, t0);
+ tcg_gen_shr_tl(bset, bset, sbit);
+ /* Displace to N_FLAG. */
+ tcg_gen_shli_tl(bset, bset, 3);
+
+ tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
+ tcg_gen_subi_tl(sbit, sbit, 1);
+ tcg_gen_and_tl(sbit, a, sbit);
+
+ tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
+ /* or in the N_FLAG. */
+ tcg_gen_or_tl(d, d, bset);
+ tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
+ /* or in the Z_FLAG. */
+ tcg_gen_ori_tl(d, d, Z_FLAG);
+ gen_set_label(l1);
+
+ tcg_temp_free(sbit);
+ tcg_temp_free(bset);
+}
+
+static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
+{
+ int l1;
+
+ l1 = gen_new_label();
+
+ /*
+ * d <<= 1
+ * if (d >= s)
+ * d -= s;
+ */
+ tcg_gen_shli_tl(d, a, 1);
+ tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
+ tcg_gen_sub_tl(d, d, b);
+ gen_set_label(l1);
}
/* Extended arithmetics on CRIS. */
if (flag)
tcg_gen_shri_tl(c, c, flag);
tcg_gen_add_tl(d, d, c);
- tcg_gen_discard_tl(c);
+ tcg_temp_free(c);
}
-static inline void t_gen_addx_carry(TCGv d)
+static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
{
- TCGv x, c;
-
- x = tcg_temp_new(TCG_TYPE_TL);
- c = tcg_temp_new(TCG_TYPE_TL);
- t_gen_mov_TN_preg(x, PR_CCS);
- tcg_gen_mov_tl(c, x);
-
- /* Propagate carry into d if X is set. Branch free. */
- tcg_gen_andi_tl(c, c, C_FLAG);
- tcg_gen_andi_tl(x, x, X_FLAG);
- tcg_gen_shri_tl(x, x, 4);
-
- tcg_gen_and_tl(x, x, c);
- tcg_gen_add_tl(d, d, x);
- tcg_gen_discard_tl(x);
- tcg_gen_discard_tl(c);
+ if (dc->flagx_known) {
+ if (dc->flags_x) {
+ TCGv c;
+
+ c = tcg_temp_new(TCG_TYPE_TL);
+ t_gen_mov_TN_preg(c, PR_CCS);
+ /* C flag is already at bit 0. */
+ tcg_gen_andi_tl(c, c, C_FLAG);
+ tcg_gen_add_tl(d, d, c);
+ tcg_temp_free(c);
+ }
+ } else {
+ TCGv x, c;
+
+ x = tcg_temp_new(TCG_TYPE_TL);
+ c = tcg_temp_new(TCG_TYPE_TL);
+ t_gen_mov_TN_preg(x, PR_CCS);
+ tcg_gen_mov_tl(c, x);
+
+ /* Propagate carry into d if X is set. Branch free. */
+ tcg_gen_andi_tl(c, c, C_FLAG);
+ tcg_gen_andi_tl(x, x, X_FLAG);
+ tcg_gen_shri_tl(x, x, 4);
+
+ tcg_gen_and_tl(x, x, c);
+ tcg_gen_add_tl(d, d, x);
+ tcg_temp_free(x);
+ tcg_temp_free(c);
+ }
}
-static inline void t_gen_subx_carry(TCGv d)
+static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
{
- TCGv x, c;
-
- x = tcg_temp_new(TCG_TYPE_TL);
- c = tcg_temp_new(TCG_TYPE_TL);
- t_gen_mov_TN_preg(x, PR_CCS);
- tcg_gen_mov_tl(c, x);
-
- /* Propagate carry into d if X is set. Branch free. */
- tcg_gen_andi_tl(c, c, C_FLAG);
- tcg_gen_andi_tl(x, x, X_FLAG);
- tcg_gen_shri_tl(x, x, 4);
-
- tcg_gen_and_tl(x, x, c);
- tcg_gen_sub_tl(d, d, x);
- tcg_gen_discard_tl(x);
- tcg_gen_discard_tl(c);
+ if (dc->flagx_known) {
+ if (dc->flags_x) {
+ TCGv c;
+
+ c = tcg_temp_new(TCG_TYPE_TL);
+ t_gen_mov_TN_preg(c, PR_CCS);
+ /* C flag is already at bit 0. */
+ tcg_gen_andi_tl(c, c, C_FLAG);
+ tcg_gen_sub_tl(d, d, c);
+ tcg_temp_free(c);
+ }
+ } else {
+ TCGv x, c;
+
+ x = tcg_temp_new(TCG_TYPE_TL);
+ c = tcg_temp_new(TCG_TYPE_TL);
+ t_gen_mov_TN_preg(x, PR_CCS);
+ tcg_gen_mov_tl(c, x);
+
+ /* Propagate carry into d if X is set. Branch free. */
+ tcg_gen_andi_tl(c, c, C_FLAG);
+ tcg_gen_andi_tl(x, x, X_FLAG);
+ tcg_gen_shri_tl(x, x, 4);
+
+ tcg_gen_and_tl(x, x, c);
+ tcg_gen_sub_tl(d, d, x);
+ tcg_temp_free(x);
+ tcg_temp_free(c);
+ }
}
/* Swap the two bytes within each half word of the s operand.
tcg_gen_shri_tl(t, org_s, 8);
tcg_gen_andi_tl(t, t, 0x00ff00ff);
tcg_gen_or_tl(d, d, t);
- tcg_gen_discard_tl(t);
- tcg_gen_discard_tl(org_s);
+ tcg_temp_free(t);
+ tcg_temp_free(org_s);
}
/* Swap the halfwords of the s operand. */
tcg_gen_shli_tl(d, t, 16);
tcg_gen_shri_tl(t, t, 16);
tcg_gen_or_tl(d, d, t);
- tcg_gen_discard_tl(t);
+ tcg_temp_free(t);
}
/* Reverse the within each byte.
tcg_gen_andi_tl(t, t, bitrev[i].mask);
tcg_gen_or_tl(d, d, t);
}
- tcg_gen_discard_tl(t);
- tcg_gen_discard_tl(org_s);
+ tcg_temp_free(t);
+ tcg_temp_free(org_s);
+}
+
+static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
+{
+ TCGv btaken;
+ int l1;
+
+ l1 = gen_new_label();
+ btaken = tcg_temp_new(TCG_TYPE_TL);
+
+ /* Conditional jmp. */
+ t_gen_mov_TN_env(btaken, btaken);
+ tcg_gen_mov_tl(env_pc, pc_false);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
+ tcg_gen_mov_tl(env_pc, pc_true);
+ gen_set_label(l1);
+
+ tcg_temp_free(btaken);
}
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
static inline void cris_clear_x_flag(DisasContext *dc)
{
- if (!dc->flagx_live
- || (dc->flagx_live && dc->flags_x)
- || dc->cc_op != CC_OP_FLAGS)
- tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
- dc->flagx_live = 1;
+ dc->flagx_known = 1;
dc->flags_x = 0;
}
-static void cris_evaluate_flags(DisasContext *dc)
+static void cris_flush_cc_state(DisasContext *dc)
{
- if (!dc->flags_live) {
- tcg_gen_movi_tl(cc_op, dc->cc_op);
+ if (dc->cc_size_uptodate != dc->cc_size) {
tcg_gen_movi_tl(cc_size, dc->cc_size);
- tcg_gen_movi_tl(cc_mask, dc->cc_mask);
+ dc->cc_size_uptodate = dc->cc_size;
+ }
+ tcg_gen_movi_tl(cc_op, dc->cc_op);
+ tcg_gen_movi_tl(cc_mask, dc->cc_mask);
+}
+
+static void cris_evaluate_flags(DisasContext *dc)
+{
+ if (!dc->flags_uptodate) {
+ cris_flush_cc_state(dc);
switch (dc->cc_op)
{
tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
break;
case CC_OP_MOVE:
+ case CC_OP_AND:
+ case CC_OP_OR:
+ case CC_OP_XOR:
+ case CC_OP_ASR:
+ case CC_OP_LSR:
+ case CC_OP_LSL:
switch (dc->cc_size)
{
case 4:
}
break;
}
- dc->flags_live = 1;
+ dc->flags_uptodate = 1;
}
}
if (mask == 0)
dc->update_cc = 0;
else
- dc->flags_live = 0;
+ dc->flags_uptodate = 0;
}
static void cris_update_cc_op(DisasContext *dc, int op, int size)
{
dc->cc_op = op;
dc->cc_size = size;
- dc->flags_live = 0;
+ dc->flags_uptodate = 0;
}
-/* op is the operation.
- T0, T1 are the operands.
- dst is the destination reg.
-*/
-static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
+static inline void cris_update_cc_x(DisasContext *dc)
+{
+ /* Save the x flag state at the time of the cc snapshot. */
+ if (dc->flagx_known) {
+ if (dc->cc_x_uptodate == (2 | dc->flags_x))
+ return;
+ tcg_gen_movi_tl(cc_x, dc->flags_x);
+ dc->cc_x_uptodate = 2 | dc->flags_x;
+ }
+ else {
+ tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
+ dc->cc_x_uptodate = 1;
+ }
+}
+
+/* Update cc prior to executing ALU op. Needs source operands untouched. */
+static void cris_pre_alu_update_cc(DisasContext *dc, int op,
+ TCGv dst, TCGv src, int size)
{
- int writeback = 1;
if (dc->update_cc) {
cris_update_cc_op(dc, op, size);
- tcg_gen_mov_tl(cc_dest, cpu_T[0]);
+ tcg_gen_mov_tl(cc_src, src);
+
+ if (op != CC_OP_MOVE
+ && op != CC_OP_AND
+ && op != CC_OP_OR
+ && op != CC_OP_XOR
+ && op != CC_OP_ASR
+ && op != CC_OP_LSR
+ && op != CC_OP_LSL)
+ tcg_gen_mov_tl(cc_dest, dst);
+
+ cris_update_cc_x(dc);
+ }
+}
- /* FIXME: This shouldn't be needed. But we don't pass the
- tests without it. Investigate. */
- t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
- t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
+/* Update cc after executing ALU op. needs the result. */
+static inline void cris_update_result(DisasContext *dc, TCGv res)
+{
+ if (dc->update_cc) {
+ if (dc->cc_size == 4 &&
+ (dc->cc_op == CC_OP_SUB
+ || dc->cc_op == CC_OP_ADD))
+ return;
+ tcg_gen_mov_tl(cc_result, res);
}
+}
+/* Returns one if the write back stage should execute. */
+static void cris_alu_op_exec(DisasContext *dc, int op,
+ TCGv dst, TCGv a, TCGv b, int size)
+{
/* Emit the ALU insns. */
switch (op)
{
case CC_OP_ADD:
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_add_tl(dst, a, b);
/* Extended arithmetics. */
- t_gen_addx_carry(cpu_T[0]);
+ t_gen_addx_carry(dc, dst);
break;
case CC_OP_ADDC:
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
+ tcg_gen_add_tl(dst, a, b);
+ t_gen_add_flag(dst, 0); /* C_FLAG. */
break;
case CC_OP_MCP:
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
+ tcg_gen_add_tl(dst, a, b);
+ t_gen_add_flag(dst, 8); /* R_FLAG. */
break;
case CC_OP_SUB:
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
- /* CRIS flag evaluation needs ~src. */
- tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
-
+ tcg_gen_sub_tl(dst, a, b);
/* Extended arithmetics. */
- t_gen_subx_carry(cpu_T[0]);
+ t_gen_subx_carry(dc, dst);
break;
case CC_OP_MOVE:
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
+ tcg_gen_mov_tl(dst, b);
break;
case CC_OP_OR:
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_or_tl(dst, a, b);
break;
case CC_OP_AND:
- tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_and_tl(dst, a, b);
break;
case CC_OP_XOR:
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ tcg_gen_xor_tl(dst, a, b);
break;
case CC_OP_LSL:
- t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ t_gen_lsl(dst, a, b);
break;
case CC_OP_LSR:
- t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
+ t_gen_lsr(dst, a, b);
break;
case CC_OP_ASR:
- t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
+ t_gen_asr(dst, a, b);
break;
case CC_OP_NEG:
- /* Hopefully the TCG backend recognizes this pattern
- and makes a real neg out of it. */
- tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_neg_tl(dst, b);
/* Extended arithmetics. */
- t_gen_subx_carry(cpu_T[0]);
+ t_gen_subx_carry(dc, dst);
break;
case CC_OP_LZ:
- gen_op_lz_T0_T1();
+ t_gen_lz_i32(dst, b);
break;
case CC_OP_BTST:
- gen_op_btst_T0_T1();
- writeback = 0;
+ t_gen_btst(dst, a, b);
break;
case CC_OP_MULS:
- {
- TCGv mof;
- mof = tcg_temp_new(TCG_TYPE_TL);
- t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
- t_gen_mov_preg_TN(PR_MOF, mof);
- tcg_gen_discard_tl(mof);
- }
- break;
+ t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
+ break;
case CC_OP_MULU:
- {
- TCGv mof;
- mof = tcg_temp_new(TCG_TYPE_TL);
- t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
- t_gen_mov_preg_TN(PR_MOF, mof);
- tcg_gen_discard_tl(mof);
- }
- break;
+ t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
+ break;
case CC_OP_DSTEP:
- gen_op_dstep_T0_T1();
+ t_gen_cris_dstep(dst, a, b);
break;
case CC_OP_BOUND:
{
int l1;
l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_LEU,
- cpu_T[0], cpu_T[1], l1);
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
+ tcg_gen_mov_tl(dst, a);
+ tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
+ tcg_gen_mov_tl(dst, b);
gen_set_label(l1);
}
break;
case CC_OP_CMP:
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- /* CRIS flag evaluation needs ~src. */
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
- /* CRIS flag evaluation needs ~src. */
- tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
-
+ tcg_gen_sub_tl(dst, a, b);
/* Extended arithmetics. */
- t_gen_subx_carry(cpu_T[0]);
- writeback = 0;
+ t_gen_subx_carry(dc, dst);
break;
default:
fprintf (logfile, "illegal ALU op.\n");
break;
}
- if (dc->update_cc)
- tcg_gen_mov_tl(cc_src, cpu_T[1]);
-
if (size == 1)
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
+ tcg_gen_andi_tl(dst, dst, 0xff);
else if (size == 2)
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
+ tcg_gen_andi_tl(dst, dst, 0xffff);
+}
- /* Writeback. */
- if (writeback) {
- if (size == 4)
- t_gen_mov_reg_TN(rd, cpu_T[0]);
- else {
- tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
- t_gen_mov_TN_reg(cpu_T[0], rd);
- if (size == 1)
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
- else
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- t_gen_mov_reg_TN(rd, cpu_T[0]);
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- }
+static void cris_alu(DisasContext *dc, int op,
+ TCGv d, TCGv op_a, TCGv op_b, int size)
+{
+ TCGv tmp;
+ int writeback;
+
+ writeback = 1;
+ tmp = cpu_T[0];
+ if (op == CC_OP_CMP)
+ writeback = 0;
+ else if (size == 4) {
+ tmp = d;
+ writeback = 0;
}
- if (dc->update_cc)
- tcg_gen_mov_tl(cc_result, cpu_T[0]);
- {
- /* TODO: Optimize this. */
- if (!dc->flagx_live)
- cris_evaluate_flags(dc);
+ cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
+ cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
+ cris_update_result(dc, tmp);
+
+ /* Writeback. */
+ if (writeback) {
+ if (size == 1)
+ tcg_gen_andi_tl(d, d, ~0xff);
+ else
+ tcg_gen_andi_tl(d, d, ~0xffff);
+ tcg_gen_or_tl(d, d, tmp);
}
}
{
if (dc->update_cc) {
switch (dc->cc_op) {
+ case CC_OP_ADDC: return 1;
case CC_OP_ADD: return 1;
case CC_OP_SUB: return 1;
+ case CC_OP_DSTEP: return 1;
case CC_OP_LSL: return 1;
case CC_OP_LSR: return 1;
case CC_OP_ASR: return 1;
case CC_OP_CMP: return 1;
+ case CC_OP_NEG: return 1;
+ case CC_OP_OR: return 1;
+ case CC_OP_XOR: return 1;
+ case CC_OP_MULU: return 1;
+ case CC_OP_MULS: return 1;
default:
return 0;
}
int arith_opt;
/* TODO: optimize more condition codes. */
- arith_opt = arith_cc(dc) && !dc->flags_live;
+
+ /*
+ * If the flags are live, we've gotta look into the bits of CCS.
+ * Otherwise, if we just did an arithmetic operation we try to
+ * evaluate the condition code faster.
+ *
+ * When this function is done, T0 should be non-zero if the condition
+ * code is true.
+ */
+ arith_opt = arith_cc(dc) && !dc->flags_uptodate;
switch (cond) {
case CC_EQ:
- if (arith_opt)
- gen_op_tst_cc_eq_fast ();
+ if (arith_opt) {
+ /* If cc_result is zero, T0 should be
+ non-zero otherwise T0 should be zero. */
+ int l1;
+ l1 = gen_new_label();
+ tcg_gen_movi_tl(cpu_T[0], 0);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
+ 0, l1);
+ tcg_gen_movi_tl(cpu_T[0], 1);
+ gen_set_label(l1);
+ }
else {
cris_evaluate_flags(dc);
- gen_op_tst_cc_eq ();
+ tcg_gen_andi_tl(cpu_T[0],
+ cpu_PR[PR_CCS], Z_FLAG);
}
break;
case CC_NE:
if (arith_opt)
- gen_op_tst_cc_ne_fast ();
+ tcg_gen_mov_tl(cpu_T[0], cc_result);
else {
cris_evaluate_flags(dc);
- gen_op_tst_cc_ne ();
+ tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
+ Z_FLAG);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
}
break;
case CC_CS:
cris_evaluate_flags(dc);
- gen_op_tst_cc_cs ();
+ tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
break;
case CC_CC:
cris_evaluate_flags(dc);
- gen_op_tst_cc_cc ();
+ tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
+ C_FLAG);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
break;
case CC_VS:
cris_evaluate_flags(dc);
- gen_op_tst_cc_vs ();
+ tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
break;
case CC_VC:
cris_evaluate_flags(dc);
- gen_op_tst_cc_vc ();
+ tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
+ V_FLAG);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
break;
case CC_PL:
if (arith_opt)
- gen_op_tst_cc_pl_fast ();
+ tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
else {
cris_evaluate_flags(dc);
- gen_op_tst_cc_pl ();
+ tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
+ N_FLAG);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
}
break;
case CC_MI:
- if (arith_opt)
- gen_op_tst_cc_mi_fast ();
+ if (arith_opt) {
+ tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
+ tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
+ }
else {
cris_evaluate_flags(dc);
- gen_op_tst_cc_mi ();
+ tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
+ N_FLAG);
}
break;
case CC_LS:
cris_evaluate_flags(dc);
- gen_op_tst_cc_ls ();
+ tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
+ C_FLAG | Z_FLAG);
break;
case CC_HI:
cris_evaluate_flags(dc);
- gen_op_tst_cc_hi ();
+ {
+ TCGv tmp;
+
+ tmp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
+ C_FLAG | Z_FLAG);
+ /* Overlay the C flag on top of the Z. */
+ tcg_gen_shli_tl(cpu_T[0], tmp, 2);
+ tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
+
+ tcg_temp_free(tmp);
+ }
break;
case CC_GE:
cris_evaluate_flags(dc);
- gen_op_tst_cc_ge ();
+ /* Overlay the V flag on top of the N. */
+ tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
+ tcg_gen_xor_tl(cpu_T[0],
+ cpu_PR[PR_CCS], cpu_T[0]);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
+ tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
break;
case CC_LT:
cris_evaluate_flags(dc);
- gen_op_tst_cc_lt ();
+ /* Overlay the V flag on top of the N. */
+ tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
+ tcg_gen_xor_tl(cpu_T[0],
+ cpu_PR[PR_CCS], cpu_T[0]);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
break;
case CC_GT:
cris_evaluate_flags(dc);
- gen_op_tst_cc_gt ();
+ {
+ TCGv n, z;
+
+ n = tcg_temp_new(TCG_TYPE_TL);
+ z = tcg_temp_new(TCG_TYPE_TL);
+
+ /* To avoid a shift we overlay everything on
+ the V flag. */
+ tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
+ tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
+ /* invert Z. */
+ tcg_gen_xori_tl(z, z, 2);
+
+ tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
+ tcg_gen_xori_tl(n, n, 2);
+ tcg_gen_and_tl(cpu_T[0], z, n);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
+
+ tcg_temp_free(n);
+ tcg_temp_free(z);
+ }
break;
case CC_LE:
cris_evaluate_flags(dc);
- gen_op_tst_cc_le ();
+ {
+ TCGv n, z;
+
+ n = tcg_temp_new(TCG_TYPE_TL);
+ z = tcg_temp_new(TCG_TYPE_TL);
+
+ /* To avoid a shift we overlay everything on
+ the V flag. */
+ tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
+ tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
+
+ tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
+ tcg_gen_or_tl(cpu_T[0], z, n);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
+
+ tcg_temp_free(n);
+ tcg_temp_free(z);
+ }
break;
case CC_P:
cris_evaluate_flags(dc);
- gen_op_tst_cc_p ();
+ tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
break;
case CC_A:
- cris_evaluate_flags(dc);
- gen_op_movl_T0_im (1);
+ tcg_gen_movi_tl(cpu_T[0], 1);
break;
default:
BUG();
/* This helps us re-schedule the micro-code to insns in delay-slots
before the actual jump. */
dc->delayed_branch = 2;
- dc->delayed_pc = dc->pc + offset;
- dc->bcc = cond;
if (cond != CC_A)
{
gen_tst_cc (dc, cond);
- gen_op_evaluate_bcc ();
- }
- tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
+ t_gen_mov_env_TN(btaken, cpu_T[0]);
+ } else
+ t_gen_mov_env_TN(btaken, tcg_const_tl(1));
+ tcg_gen_movi_tl(env_btarget, dc->pc + offset);
}
/* This helps us re-schedule the micro-code to insns in delay-slots
before the actual jump. */
dc->delayed_branch = 2;
- dc->dyn_jmp = 1;
- dc->bcc = CC_A;
-}
-
-void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
-{
- /* This helps us re-schedule the micro-code to insns in delay-slots
- before the actual jump. */
- dc->delayed_branch = 2;
- dc->delayed_pc = dst;
- dc->dyn_jmp = 0;
- dc->bcc = CC_A;
+ t_gen_mov_env_TN(btaken, tcg_const_tl(1));
}
void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
{
int mem_index = cpu_mmu_index(dc->env);
- /* FIXME: qemu_ld does not act as a barrier? */
- tcg_gen_helper_0_0(helper_dummy);
- cris_evaluate_flags(dc);
if (size == 1) {
if (sign)
tcg_gen_qemu_ld8s(dst, addr, mem_index);
tcg_gen_qemu_ld16u(dst, addr, mem_index);
}
else {
- tcg_gen_qemu_ld32s(dst, addr, mem_index);
+ tcg_gen_qemu_ld32u(dst, addr, mem_index);
}
}
-void gen_store_T0_T1 (DisasContext *dc, unsigned int size)
+void gen_store (DisasContext *dc, TCGv addr, TCGv val,
+ unsigned int size)
{
int mem_index = cpu_mmu_index(dc->env);
- /* FIXME: qemu_st does not act as a barrier? */
- tcg_gen_helper_0_0(helper_dummy);
- cris_evaluate_flags(dc);
-
/* Remember, operands are flipped. CRIS has reversed order. */
if (size == 1)
- tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], mem_index);
+ tcg_gen_qemu_st8(val, addr, mem_index);
else if (size == 2)
- tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], mem_index);
+ tcg_gen_qemu_st16(val, addr, mem_index);
else
- tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], mem_index);
+ tcg_gen_qemu_st32(val, addr, mem_index);
}
static inline void t_gen_sext(TCGv d, TCGv s, int size)
tcg_gen_ext8s_i32(d, s);
else if (size == 2)
tcg_gen_ext16s_i32(d, s);
- else
+ else if(d != s)
tcg_gen_mov_tl(d, s);
}
static inline void t_gen_zext(TCGv d, TCGv s, int size)
{
- /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
if (size == 1)
- tcg_gen_andi_i32(d, s, 0xff);
+ tcg_gen_ext8u_i32(d, s);
else if (size == 2)
- tcg_gen_andi_i32(d, s, 0xffff);
- else
+ tcg_gen_ext16u_i32(d, s);
+ else if (d != s)
tcg_gen_mov_tl(d, s);
}
}
#endif
-static unsigned int memsize_z(DisasContext *dc)
+static inline unsigned int memsize_z(DisasContext *dc)
{
return dc->zsize + 1;
}
-static unsigned int memsize_zz(DisasContext *dc)
+static inline unsigned int memsize_zz(DisasContext *dc)
{
switch (dc->zzsize)
{
tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
}
-
-static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
- int size, int s_ext)
+static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
+ int size, int s_ext, TCGv dst)
{
if (s_ext)
- t_gen_sext(cpu_T[1], cpu_R[rs], size);
+ t_gen_sext(dst, cpu_R[rs], size);
else
- t_gen_zext(cpu_T[1], cpu_R[rs], size);
+ t_gen_zext(dst, cpu_R[rs], size);
}
/* Prepare T0 and T1 for a register alu operation.
static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
int size, int s_ext)
{
- dec_prep_move_r(dc, rs, rd, size, s_ext);
+ dec_prep_move_r(dc, rs, rd, size, s_ext, cpu_T[1]);
if (s_ext)
t_gen_sext(cpu_T[0], cpu_R[rd], size);
t_gen_zext(cpu_T[0], cpu_R[rd], size);
}
-/* Prepare T0 and T1 for a memory + alu operation.
- s_ext decides if the operand1 should be sign-extended or zero-extended when
- needed. */
-static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
+static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
+ TCGv dst)
{
unsigned int rs, rd;
uint32_t imm;
if (memsize == 1)
insn_len++;
- imm = ldl_code(dc->pc + 2);
if (memsize != 4) {
if (s_ext) {
- imm = sign_extend(imm, (memsize * 8) - 1);
+ if (memsize == 1)
+ imm = ldsb_code(dc->pc + 2);
+ else
+ imm = ldsw_code(dc->pc + 2);
} else {
if (memsize == 1)
- imm &= 0xff;
+ imm = ldub_code(dc->pc + 2);
else
- imm &= 0xffff;
+ imm = lduw_code(dc->pc + 2);
}
- }
+ } else
+ imm = ldl_code(dc->pc + 2);
+
DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
- imm, rd, s_ext, memsize));
- tcg_gen_movi_tl(cpu_T[1], imm);
+ imm, rd, s_ext, memsize));
+ tcg_gen_movi_tl(dst, imm);
dc->postinc = 0;
} else {
- gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
+ cris_flush_cc_state(dc);
+ gen_load(dc, dst, cpu_R[rs], memsize, 0);
if (s_ext)
- t_gen_sext(cpu_T[1], cpu_T[1], memsize);
+ t_gen_sext(dst, dst, memsize);
else
- t_gen_zext(cpu_T[1], cpu_T[1], memsize);
+ t_gen_zext(dst, dst, memsize);
}
+ return insn_len;
+}
+
+/* Prepare T0 and T1 for a memory + alu operation.
+ s_ext decides if the operand1 should be sign-extended or zero-extended when
+ needed. */
+static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
+{
+ int insn_len;
+
+ insn_len = dec_prep_move_m(dc, s_ext, memsize, cpu_T[1]);
/* put dest in T0. */
- t_gen_mov_TN_reg(cpu_T[0], rd);
+ tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
return insn_len;
}
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
cris_cc_mask(dc, CC_MASK_NZVC);
- /* Fetch register operand, */
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- tcg_gen_movi_tl(cpu_T[1], dc->op1);
- crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
static unsigned int dec_moveq(DisasContext *dc)
imm = sign_extend(dc->op1, 5);
DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
- t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
+ tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
return 2;
}
static unsigned int dec_subq(DisasContext *dc)
DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
- /* Fetch register operand, */
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], dc->op1);
- crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
+ cris_alu(dc, CC_OP_SUB,
+ cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
static unsigned int dec_cmpq(DisasContext *dc)
DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], imm);
- crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_CMP,
+ cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
static unsigned int dec_andq(DisasContext *dc)
DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], imm);
- crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_AND,
+ cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
static unsigned int dec_orq(DisasContext *dc)
imm = sign_extend(dc->op1, 5);
DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], imm);
- crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_OR,
+ cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
return 2;
}
static unsigned int dec_btstq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
+
cris_cc_mask(dc, CC_MASK_NZ);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], dc->op1);
- crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
+ t_gen_mov_TN_reg(cpu_T[0], dc->op2);
+ cris_alu(dc, CC_OP_BTST,
+ cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
- dc->flags_live = 1;
+ t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
+ dc->flags_uptodate = 1;
return 2;
}
static unsigned int dec_asrq(DisasContext *dc)
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], dc->op1);
- crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_ASR,
+ cpu_R[dc->op2],
+ cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
static unsigned int dec_lslq(DisasContext *dc)
DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], dc->op1);
- crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_LSL,
+ cpu_R[dc->op2],
+ cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
static unsigned int dec_lsrq(DisasContext *dc)
DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- t_gen_mov_TN_im(cpu_T[1], dc->op1);
- crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_LSR,
+ cpu_R[dc->op2],
+ cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
+ if (size == 4) {
+ dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
+ cris_cc_mask(dc, CC_MASK_NZ);
+ cris_update_cc_op(dc, CC_OP_MOVE, 4);
+ cris_update_cc_x(dc);
+ cris_update_result(dc, cpu_R[dc->op2]);
+ }
+ else {
+ dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2],
+ cpu_R[dc->op2], cpu_T[1], size);
+ }
return 2;
}
if (cond != CC_A)
{
+ int l1;
+
gen_tst_cc (dc, cond);
- tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
+
+ l1 = gen_new_label();
+ tcg_gen_movi_tl(cpu_R[dc->op1], 0);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
+ tcg_gen_movi_tl(cpu_R[dc->op1], 1);
+ gen_set_label(l1);
}
else
- tcg_gen_movi_tl(cpu_T[1], 1);
+ tcg_gen_movi_tl(cpu_R[dc->op1], 1);
cris_cc_mask(dc, 0);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
+
+ cris_alu(dc, CC_OP_AND,
+ cpu_R[dc->op2],
+ cpu_R[dc->op2], cpu_T[1], size);
return 2;
}
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
- crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
+ cris_alu(dc, CC_OP_LZ,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
return 2;
}
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
- crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
+
+ cris_alu(dc, CC_OP_LSL,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
- crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
+
+ cris_alu(dc, CC_OP_LSR,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
- crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
+
+ cris_alu(dc, CC_OP_ASR,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZV);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
- t_gen_sext(cpu_T[0], cpu_T[0], size);
- crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_MULS,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZV);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- t_gen_zext(cpu_T[0], cpu_T[0], size);
- crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_MULU,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
return 2;
}
{
DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- t_gen_mov_TN_reg(cpu_T[1], dc->op1);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
+ cris_alu(dc, CC_OP_DSTEP,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
return 2;
}
BUG_ON(size != 4); /* xor is dword. */
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
+
+ cris_alu(dc, CC_OP_XOR,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
return 2;
}
DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- /* TODO: needs optmimization. */
- dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- /* rd should be 4. */
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
+ dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
+ cris_alu(dc, CC_OP_BOUND,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
+
+ cris_alu(dc, CC_OP_CMP,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
DIS(fprintf (logfile, "abs $r%u, $r%u\n",
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
+ dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0, cpu_T[1]);
/* TODO: consider a branch free approach. */
l1 = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
- tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
+ tcg_gen_brcondi_tl(TCG_COND_GE, cpu_T[1], 0, l1);
+ tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
gen_set_label(l1);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
+
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
cris_evaluate_flags(dc);
cris_cc_mask(dc, CC_MASK_NZVC);
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
- crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
+ cris_alu(dc, CC_OP_ADDC,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
return 2;
}
dc->op2, dc->op1));
cris_evaluate_flags(dc);
cris_cc_mask(dc, CC_MASK_RNZV);
- t_gen_mov_TN_reg(cpu_T[0], dc->op1);
- t_gen_mov_TN_preg(cpu_T[1], dc->op2);
- crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
+ cris_alu(dc, CC_OP_MCP,
+ cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
return 2;
}
static unsigned int dec_swap_r(DisasContext *dc)
{
- DIS(char modename[4]);
+#if DISAS_CRIS
+ char modename[4];
+#endif
DIS(fprintf (logfile, "swap%s $r%u\n",
swapmode_name(dc->op2, modename), dc->op1));
cris_cc_mask(dc, CC_MASK_NZ);
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
if (dc->op2 & 8)
- tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
+ tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
if (dc->op2 & 4)
t_gen_swapw(cpu_T[0], cpu_T[0]);
if (dc->op2 & 2)
t_gen_swapb(cpu_T[0], cpu_T[0]);
if (dc->op2 & 1)
t_gen_swapr(cpu_T[0], cpu_T[0]);
- tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0], 4);
+
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
+
+ cris_alu(dc, CC_OP_OR,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
cris_cc_mask(dc, 0);
- dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
- t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
+ tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
+ tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[0]);
return 2;
}
DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
cris_cc_mask(dc, 0);
- dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
- t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
-
- tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
- t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
+ tcg_gen_shl_tl(cpu_T[0], cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
+ tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], cpu_T[0]);
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
+
+ cris_alu(dc, CC_OP_NEG,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
- crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
+ cris_alu(dc, CC_OP_BTST,
+ cpu_T[0], cpu_T[0], cpu_T[1], 4);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
- dc->flags_live = 1;
+ t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
+ dc->flags_uptodate = 1;
return 2;
}
memsize_char(size), dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
+ cris_alu(dc, CC_OP_SUB,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], size);
return 2;
}
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
- dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
+ dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_T[1]);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
return 2;
}
cris_cc_mask(dc, CC_MASK_NZ);
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
/* Size can only be qi or hi. */
- t_gen_sext(cpu_T[1], cpu_T[0], size);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
+ t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
return 2;
}
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
- t_gen_mov_TN_reg(cpu_T[1], dc->op1);
/* Size can only be qi or hi. */
- t_gen_zext(cpu_T[1], cpu_T[1], size);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
+ t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
return 2;
}
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
- t_gen_mov_TN_reg(cpu_T[1], dc->op1);
/* Size can only be qi or hi. */
- t_gen_sext(cpu_T[1], cpu_T[1], size);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
-
- crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
+ t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
return 2;
}
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
- t_gen_mov_TN_reg(cpu_T[1], dc->op1);
/* Size can only be qi or hi. */
- t_gen_zext(cpu_T[1], cpu_T[1], size);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
+ t_gen_zext(cpu_T[1], cpu_R[dc->op1], size);
+ cris_alu(dc, CC_OP_SUB,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
return 2;
}
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZVC);
- t_gen_mov_TN_reg(cpu_T[1], dc->op1);
/* Size can only be qi or hi. */
- t_gen_sext(cpu_T[1], cpu_T[1], size);
- t_gen_mov_TN_reg(cpu_T[0], dc->op2);
- crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
+ t_gen_sext(cpu_T[1], cpu_R[dc->op1], size);
+ cris_alu(dc, CC_OP_SUB,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
return 2;
}
flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
| EXTRACT_FIELD(dc->ir, 0, 3);
DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
- if (set && flags == 0)
+ if (set && flags == 0) {
DIS(fprintf (logfile, "nop\n"));
- else if (!set && (flags & 0x20))
+ return 2;
+ } else if (!set && (flags & 0x20)) {
DIS(fprintf (logfile, "di\n"));
- else
+ }
+ else {
DIS(fprintf (logfile, "%sf %x\n",
- set ? "set" : "clr",
+ set ? "set" : "clr",
flags));
+ }
if (set && (flags & X_FLAG)) {
- dc->flagx_live = 1;
- dc->flags_x = 1;
+ dc->flagx_known = 1;
+ dc->flags_x = X_FLAG;
+ } else {
+ dc->flagx_known = 0;
}
/* Simply decode the flags. */
cris_evaluate_flags (dc);
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
+ cris_update_cc_x(dc);
tcg_gen_movi_tl(cc_op, dc->cc_op);
- if (set)
- gen_op_setf(flags);
+ if (set) {
+ if (!dc->user && (flags & U_FLAG)) {
+ /* Enter user mode. */
+ t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
+ tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
+ dc->is_jmp = DISAS_NEXT;
+ }
+ tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
+ }
else
- gen_op_clrf(flags);
- dc->flags_live = 1;
+ tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
+
+ dc->flags_uptodate = 1;
dc->clear_x = 0;
return 2;
}
{
DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
cris_cc_mask(dc, 0);
- t_gen_mov_TN_reg(cpu_T[0], dc->op1);
- gen_op_movl_sreg_T0(dc->op2);
-
-#if !defined(CONFIG_USER_ONLY)
- if (dc->op2 == 6)
- gen_op_movl_tlb_hi_T0();
- else if (dc->op2 == 5) { /* srs is checked at runtime. */
- tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]);
- gen_op_movl_tlb_lo_T0();
- }
-#endif
+ tcg_gen_helper_0_2(helper_movl_sreg_reg,
+ tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
return 2;
}
static unsigned int dec_move_sr(DisasContext *dc)
{
DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
cris_cc_mask(dc, 0);
- gen_op_movl_T0_sreg(dc->op2);
- tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
+ tcg_gen_helper_0_2(helper_movl_reg_sreg,
+ tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
return 2;
}
+
static unsigned int dec_move_rp(DisasContext *dc)
{
DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
else
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
- t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
+ t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
if (dc->op2 == PR_CCS) {
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
- dc->flags_live = 1;
+ dc->flags_uptodate = 1;
}
return 2;
}
t_gen_mov_TN_preg(cpu_T[1], dc->op2);
} else
t_gen_mov_TN_preg(cpu_T[1], dc->op2);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[1],
+ preg_sizes[dc->op2]);
return 2;
}
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
- insn_len = dec_prep_alu_m(dc, 0, memsize);
- cris_cc_mask(dc, CC_MASK_NZ);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
+ if (memsize == 4) {
+ insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
+ cris_cc_mask(dc, CC_MASK_NZ);
+ cris_update_cc_op(dc, CC_OP_MOVE, 4);
+ cris_update_cc_x(dc);
+ cris_update_result(dc, cpu_R[dc->op2]);
+ }
+ else {
+ insn_len = dec_prep_move_m(dc, 0, memsize, cpu_T[1]);
+ cris_cc_mask(dc, CC_MASK_NZ);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], memsize);
+ }
do_postinc(dc, memsize);
return insn_len;
}
/* sign extend. */
insn_len = dec_prep_alu_m(dc, 1, memsize);
cris_cc_mask(dc, CC_MASK_NZ);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
/* sign extend. */
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
/* sign extend. */
insn_len = dec_prep_alu_m(dc, 1, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
/* sign extend. */
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
+ cris_alu(dc, CC_OP_SUB,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
/* sign extend. */
insn_len = dec_prep_alu_m(dc, 1, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
+ cris_alu(dc, CC_OP_SUB,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZ);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
+ cris_alu(dc, CC_OP_MOVE,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
+ cris_alu(dc, CC_OP_CMP,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 1, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
+ cris_alu(dc, CC_OP_CMP,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
+ memsize_zz(dc));
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
+ cris_alu(dc, CC_OP_CMP,
+ cpu_R[dc->op2], cpu_R[dc->op2], cpu_T[1],
+ memsize_zz(dc));
do_postinc(dc, memsize);
return insn_len;
}
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
+ cris_evaluate_flags(dc);
+
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZ);
- gen_op_clrf(3);
+ tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- tcg_gen_movi_tl(cpu_T[1], 0);
- crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
+ cris_alu(dc, CC_OP_CMP,
+ cpu_R[dc->op2], cpu_T[1], tcg_const_tl(0),
+ memsize_zz(dc));
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZ);
- crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
+ cris_alu(dc, CC_OP_AND,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1],
+ memsize_zz(dc));
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1],
+ memsize_zz(dc));
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 1, memsize);
cris_cc_mask(dc, 0);
- crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
+ cris_alu(dc, CC_OP_ADD,
+ cpu_R[R_ACR], cpu_T[0], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZ);
- crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
+ cris_alu(dc, CC_OP_BOUND,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
do_postinc(dc, memsize);
return insn_len;
}
cris_evaluate_flags(dc);
insn_len = dec_prep_alu_m(dc, 0, 4);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
+ cris_alu(dc, CC_OP_ADDC,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], 4);
do_postinc(dc, 4);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZVC);
- crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
+ cris_alu(dc, CC_OP_SUB,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize);
do_postinc(dc, memsize);
return insn_len;
}
insn_len = dec_prep_alu_m(dc, 0, memsize);
cris_cc_mask(dc, CC_MASK_NZ);
- crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
+ cris_alu(dc, CC_OP_OR,
+ cpu_R[dc->op2], cpu_T[0], cpu_T[1], memsize_zz(dc));
do_postinc(dc, memsize);
return insn_len;
}
}
}
- t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
+ t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
do_postinc(dc, memsize);
return insn_len;
dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
/* prepare store. Address in T0, value in T1. */
+ if (dc->op2 == PR_CCS)
+ cris_evaluate_flags(dc);
t_gen_mov_TN_preg(cpu_T[1], dc->op2);
- t_gen_mov_TN_reg(cpu_T[0], dc->op1);
- gen_store_T0_T1(dc, memsize);
+ cris_flush_cc_state(dc);
+ gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
+
cris_cc_mask(dc, 0);
if (dc->postinc)
- {
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
- t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
- }
+ tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
return 2;
}
static unsigned int dec_movem_mr(DisasContext *dc)
{
+ TCGv tmp[16];
int i;
DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
dc->postinc ? "+]" : "]", dc->op2));
/* fetch the address into T0 and T1. */
- t_gen_mov_TN_reg(cpu_T[1], dc->op1);
+ cris_flush_cc_state(dc);
for (i = 0; i <= dc->op2; i++) {
+ tmp[i] = tcg_temp_new(TCG_TYPE_TL);
/* Perform the load onto regnum i. Always dword wide. */
- tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
- gen_load(dc, cpu_R[i], cpu_T[1], 4, 0);
- tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4);
+ tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
+ gen_load(dc, tmp[i], cpu_T[0], 4, 0);
}
+
+ for (i = 0; i <= dc->op2; i++) {
+ tcg_gen_mov_tl(cpu_R[i], tmp[i]);
+ tcg_temp_free(tmp[i]);
+ }
+
/* writeback the updated pointer value. */
if (dc->postinc)
- t_gen_mov_reg_TN(dc->op1, cpu_T[1]);
+ tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
/* gen_load might want to evaluate the previous insns flags. */
cris_cc_mask(dc, 0);
static unsigned int dec_movem_rm(DisasContext *dc)
{
+ TCGv tmp;
int i;
DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
dc->postinc ? "+]" : "]"));
+ cris_flush_cc_state(dc);
+
+ tmp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(tmp, 4);
+ tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op1]);
for (i = 0; i <= dc->op2; i++) {
- /* Fetch register i into T1. */
- t_gen_mov_TN_reg(cpu_T[1], i);
- /* Fetch the address into T0. */
- t_gen_mov_TN_reg(cpu_T[0], dc->op1);
- /* Displace it. */
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4);
+ /* Displace addr. */
/* Perform the store. */
- gen_store_T0_T1(dc, 4);
- }
- if (dc->postinc) {
- /* T0 should point to the last written addr, advance one more
- step. */
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4);
- /* writeback the updated pointer value. */
- t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
+ gen_store(dc, cpu_T[0], cpu_R[i], 4);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], tmp);
}
+ if (dc->postinc)
+ tcg_gen_mov_tl(cpu_R[dc->op1], cpu_T[0]);
cris_cc_mask(dc, 0);
+ tcg_temp_free(tmp);
return 2;
}
memsize, dc->op2, dc->op1));
/* prepare store. */
- t_gen_mov_TN_reg(cpu_T[0], dc->op1);
- t_gen_mov_TN_reg(cpu_T[1], dc->op2);
- gen_store_T0_T1(dc, memsize);
+ cris_flush_cc_state(dc);
+ gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
+
if (dc->postinc)
- {
- tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
- t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
- }
+ tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
cris_cc_mask(dc, 0);
return 2;
}
DIS(fprintf (logfile, "lapcq %x, $r%u\n",
dc->pc + dc->op1*2, dc->op2));
cris_cc_mask(dc, 0);
- tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
- crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
+ tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
return 2;
}
static unsigned int dec_jump_p(DisasContext *dc)
{
DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
- cris_cc_mask(dc, 0);
+ if (dc->op2 == PR_CCS)
+ cris_evaluate_flags(dc);
t_gen_mov_TN_preg(cpu_T[0], dc->op2);
/* rete will often have low bit set to indicate delayslot. */
tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
+ cris_cc_mask(dc, 0);
cris_prepare_dyn_jmp(dc);
return 2;
}
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
if (dc->op2 > 15)
abort();
- tcg_gen_movi_tl(cpu_PR[dc->op2], dc->pc + 4);
+ t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
cris_prepare_dyn_jmp(dc);
return 2;
DIS(fprintf (logfile, "jas 0x%x\n", imm));
cris_cc_mask(dc, 0);
- /* Stor the return address in Pd. */
+ /* Store the return address in Pd. */
tcg_gen_movi_tl(env_btarget, imm);
- t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
+ t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
cris_prepare_dyn_jmp(dc);
return 6;
}
DIS(fprintf (logfile, "jasc 0x%x\n", imm));
cris_cc_mask(dc, 0);
- /* Stor the return address in Pd. */
+ /* Store the return address in Pd. */
tcg_gen_movi_tl(cpu_T[0], imm);
- t_gen_mov_env_TN(btarget, cpu_T[0]);
+ tcg_gen_mov_tl(env_btarget, cpu_T[0]);
tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
- t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
+ t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
cris_prepare_dyn_jmp(dc);
return 6;
}
{
DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
cris_cc_mask(dc, 0);
- /* Stor the return address in Pd. */
+ /* Store the return address in Pd. */
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
- t_gen_mov_env_TN(btarget, cpu_T[0]);
+ tcg_gen_mov_tl(env_btarget, cpu_T[0]);
tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
- t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
+ t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
cris_prepare_dyn_jmp(dc);
return 2;
}
int32_t offset;
uint32_t cond = dc->op2;
- offset = ldl_code(dc->pc + 2);
- offset = sign_extend(offset, 15);
+ offset = ldsw_code(dc->pc + 2);
DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
cc_name(cond), offset,
cris_cc_mask(dc, 0);
/* Stor the return address in Pd. */
tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
- t_gen_mov_env_TN(btarget, cpu_T[0]);
+ tcg_gen_mov_tl(env_btarget, cpu_T[0]);
tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
- t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
+ t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
cris_prepare_dyn_jmp(dc);
return 6;
}
cris_cc_mask(dc, 0);
/* Stor the return address in Pd. */
tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
- t_gen_mov_env_TN(btarget, cpu_T[0]);
+ tcg_gen_mov_tl(env_btarget, cpu_T[0]);
tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
- t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
+ t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
cris_prepare_dyn_jmp(dc);
return 6;
}
case 2:
/* rfe. */
cris_evaluate_flags(dc);
- gen_op_ccs_rshift();
- /* FIXME: don't set the P-FLAG if R is set. */
- tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], P_FLAG);
- /* Debug helper. */
tcg_gen_helper_0_0(helper_rfe);
dc->is_jmp = DISAS_UPDATE;
break;
tcg_gen_movi_tl(cpu_T[0], dc->pc);
t_gen_mov_env_TN(pc, cpu_T[0]);
/* Breaks start at 16 in the exception vector. */
- gen_op_break_im(dc->op1 + 16);
+ t_gen_mov_env_TN(trap_vector,
+ tcg_const_tl(dc->op1 + 16));
+ t_gen_raise_exception(EXCP_BREAK);
dc->is_jmp = DISAS_UPDATE;
break;
default:
cris_decoder(DisasContext *dc)
{
unsigned int insn_len = 2;
- uint32_t tmp;
int i;
/* Load a halfword onto the instruction register. */
- tmp = ldl_code(dc->pc);
- dc->ir = tmp & 0xffff;
+ dc->ir = lduw_code(dc->pc);
/* Now decode it. */
dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
cris_evaluate_flags (dc);
tcg_gen_movi_tl(cpu_T[0], dc->pc);
t_gen_mov_env_TN(pc, cpu_T[0]);
- gen_op_debug();
+ t_gen_raise_exception(EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
}
}
}
}
+
+/*
+ * Delay slots on QEMU/CRIS.
+ *
+ * If an exception hits on a delayslot, the core will let ERP (the Exception
+ * Return Pointer) point to the branch (the previous) insn and set the lsb to
+ * to give SW a hint that the exception actually hit on the dslot.
+ *
+ * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
+ * the core and any jmp to an odd addresses will mask off that lsb. It is
+ * simply there to let sw know there was an exception on a dslot.
+ *
+ * When the software returns from an exception, the branch will re-execute.
+ * On QEMU care needs to be taken when a branch+delayslot sequence is broken
+ * and the branch and delayslot dont share pages.
+ *
+ * The TB contaning the branch insn will set up env->btarget and evaluate
+ * env->btaken. When the translation loop exits we will note that the branch
+ * sequence is broken and let env->dslot be the size of the branch insn (those
+ * vary in length).
+ *
+ * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
+ * set). It will also expect to have env->dslot setup with the size of the
+ * delay slot so that env->pc - env->dslot point to the branch insn. This TB
+ * will execute the dslot and take the branch, either to btarget or just one
+ * insn ahead.
+ *
+ * When exceptions occur, we check for env->dslot in do_interrupt to detect
+ * broken branch sequences and setup $erp accordingly (i.e let it point to the
+ * branch and set lsb). Then env->dslot gets cleared so that the exception
+ * handler can enter. When returning from exceptions (jump $erp) the lsb gets
+ * masked off and we will reexecute the branch insn.
+ *
+ */
+
/* generate intermediate code for basic block 'tb'. */
-struct DisasContext ctx;
static int
gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
int search_pc)
uint32_t pc_start;
unsigned int insn_len;
int j, lj;
+ struct DisasContext ctx;
struct DisasContext *dc = &ctx;
uint32_t next_page_start;
if (!logfile)
logfile = stderr;
- if (tb->pc & 1)
- cpu_abort(env, "unaligned pc=%x erp=%x\n",
- env->pc, env->pregs[PR_ERP]);
- pc_start = tb->pc;
+ /* Odd PC indicates that branch is rexecuting due to exception in the
+ * delayslot, like in real hw.
+ */
+ pc_start = tb->pc & ~1;
dc->env = env;
dc->tb = tb;
dc->ppc = pc_start;
dc->pc = pc_start;
dc->singlestep_enabled = env->singlestep_enabled;
- dc->flags_live = 1;
- dc->flagx_live = 0;
- dc->flags_x = 0;
+ dc->flags_uptodate = 1;
+ dc->flagx_known = 1;
+ dc->flags_x = tb->flags & X_FLAG;
+ dc->cc_x_uptodate = 0;
dc->cc_mask = 0;
+ dc->update_cc = 0;
+
cris_update_cc_op(dc, CC_OP_FLAGS, 4);
+ dc->cc_size_uptodate = -1;
- dc->user = env->pregs[PR_CCS] & U_FLAG;
- dc->delayed_branch = 0;
+ /* Decode TB flags. */
+ dc->user = tb->flags & U_FLAG;
+ dc->delayed_branch = !!(tb->flags & 7);
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile,
- "search=%d pc=%x ccs=%x pid=%x usp=%x\n"
+ "srch=%d pc=%x %x bt=%x ds=%lld ccs=%x\n"
+ "pid=%x usp=%x\n"
"%x.%x.%x.%x\n"
"%x.%x.%x.%x\n"
"%x.%x.%x.%x\n"
"%x.%x.%x.%x\n",
- search_pc, env->pc, env->pregs[PR_CCS],
+ search_pc, dc->pc, dc->ppc,
+ env->btarget, tb->flags & 7,
+ env->pregs[PR_CCS],
env->pregs[PR_PID], env->pregs[PR_USP],
env->regs[0], env->regs[1], env->regs[2], env->regs[3],
env->regs[4], env->regs[5], env->regs[6], env->regs[7],
while (lj < j)
gen_opc_instr_start[lj++] = 0;
}
- if (dc->delayed_branch == 1) {
+ if (dc->delayed_branch == 1)
gen_opc_pc[lj] = dc->ppc | 1;
- gen_opc_instr_start[lj] = 0;
- }
- else {
+ else
gen_opc_pc[lj] = dc->pc;
- gen_opc_instr_start[lj] = 1;
- }
+ gen_opc_instr_start[lj] = 1;
+ }
+
+ /* Pretty disas. */
+ DIS(fprintf(logfile, "%x ", dc->pc));
+ if (search_pc) {
+ DIS(fprintf(logfile, "%x ", dc->pc));
}
dc->clear_x = 1;
+ if (unlikely(loglevel & CPU_LOG_TB_OP))
+ tcg_gen_debug_insn_start(dc->pc);
insn_len = cris_decoder(dc);
- STATS(gen_op_exec_insn());
dc->ppc = dc->pc;
dc->pc += insn_len;
if (dc->clear_x)
actually genereating any host code, the simulator will just
loop doing nothing for on this program location. */
if (dc->delayed_branch) {
+ t_gen_mov_env_TN(dslot, tcg_const_tl(0));
dc->delayed_branch--;
if (dc->delayed_branch == 0)
{
- if (dc->bcc == CC_A) {
- gen_op_jmp1 ();
- dc->is_jmp = DISAS_JUMP;
- }
- else {
- /* Conditional jmp. */
- gen_op_cc_jmp (dc->delayed_pc, dc->pc);
- dc->is_jmp = DISAS_JUMP;
- }
+ t_gen_cc_jmp(env_btarget,
+ tcg_const_tl(dc->pc));
+ dc->is_jmp = DISAS_JUMP;
}
}
- if (env->singlestep_enabled)
+ /* If we are rexecuting a branch due to exceptions on
+ delay slots dont break. */
+ if (!(tb->pc & 1) && env->singlestep_enabled)
break;
} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
- && ((dc->pc < next_page_start) || dc->delayed_branch));
+ && (dc->pc < next_page_start));
+ /* Broken branch+delayslot sequence. */
if (dc->delayed_branch == 1) {
- /* Reexecute the last insn. */
- dc->pc = dc->ppc;
+ /* Set env->dslot to the size of the branch insn. */
+ t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
}
if (!dc->is_jmp) {
- D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
+ D(fprintf(logfile, "!jmp pc=%x jmp=%d db=%d\n", dc->pc,
dc->is_jmp, dc->delayed_branch));
/* T0 and env_pc should hold the new pc. */
tcg_gen_movi_tl(cpu_T[0], dc->pc);
cris_evaluate_flags (dc);
done:
if (__builtin_expect(env->singlestep_enabled, 0)) {
- gen_op_debug();
+ t_gen_raise_exception(EXCP_DEBUG);
} else {
switch(dc->is_jmp) {
case DISAS_NEXT:
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "--------------\n");
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
- target_disas(logfile, pc_start, dc->pc + 4 - pc_start, 0);
+ target_disas(logfile, pc_start, dc->pc - pc_start, 0);
fprintf(logfile, "\nisize=%d osize=%d\n",
dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
}
return;
cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
- "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
- "debug=%x %x %x\n",
+ "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
env->cc_op,
- env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
- env->debug1, env->debug2, env->debug3);
+ env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
+
for (i = 0; i < 16; i++) {
cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
}
-static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
-{
-}
-
CPUCRISState *cpu_cris_init (const char *cpu_model)
{
CPUCRISState *env;
return NULL;
cpu_exec_init(env);
- tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
#if TARGET_LONG_BITS > HOST_LONG_BITS
cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
#endif
- cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ cc_x = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ offsetof(CPUState, cc_x), "cc_x");
+ cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
offsetof(CPUState, cc_src), "cc_src");
- cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
- offsetof(CPUState, cc_dest),
+ cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ offsetof(CPUState, cc_dest),
"cc_dest");
- cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
- offsetof(CPUState, cc_result),
+ cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ offsetof(CPUState, cc_result),
"cc_result");
- cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
offsetof(CPUState, cc_op), "cc_op");
- cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
- offsetof(CPUState, cc_size),
+ cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ offsetof(CPUState, cc_size),
"cc_size");
- cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
offsetof(CPUState, cc_mask),
"cc_mask");
env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
- offsetof(CPUState, pc),
- "pc");
- env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
- offsetof(CPUState, btarget),
- "btarget");
+ offsetof(CPUState, pc),
+ "pc");
+ env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ offsetof(CPUState, btarget),
+ "btarget");
for (i = 0; i < 16; i++) {
- cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
- offsetof(CPUState, regs[i]),
+ cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ offsetof(CPUState, regs[i]),
regnames[i]);
}
for (i = 0; i < 16; i++) {
- cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
- offsetof(CPUState, pregs[i]),
+ cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
+ offsetof(CPUState, pregs[i]),
pregnames[i]);
}
- TCG_HELPER(helper_tlb_update);
- TCG_HELPER(helper_tlb_flush);
- TCG_HELPER(helper_rfe);
+ TCG_HELPER(helper_raise_exception);
TCG_HELPER(helper_store);
TCG_HELPER(helper_dump);
TCG_HELPER(helper_dummy);
+ TCG_HELPER(helper_tlb_flush_pid);
+ TCG_HELPER(helper_movl_sreg_reg);
+ TCG_HELPER(helper_movl_reg_sreg);
+ TCG_HELPER(helper_rfe);
+
TCG_HELPER(helper_evaluate_flags_muls);
TCG_HELPER(helper_evaluate_flags_mulu);
TCG_HELPER(helper_evaluate_flags_mcp);
TCG_HELPER(helper_evaluate_flags_move_4);
TCG_HELPER(helper_evaluate_flags_move_2);
TCG_HELPER(helper_evaluate_flags);
+ TCG_HELPER(helper_top_evaluate_flags);
cpu_reset(env);
return env;
void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
unsigned long searched_pc, int pc_pos, void *puc)
{
- env->pc = gen_opc_pc[pc_pos];
+ env->pc = gen_opc_pc[pc_pos];
}
projects / qemu.git / blobdiff