/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Not strictly an SPR */
vscr_init(env, 0x00010000);
PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x00000000000FD201ULL;
pcc->mmu_model = POWERPC_MMU_REAL;
pcc->excp_model = POWERPC_EXCP_40x;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x00000000001FD231ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
pcc->excp_model = POWERPC_EXCP_40x;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x00000000001FD631ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
pcc->excp_model = POWERPC_EXCP_40x;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x00000000001FD231ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
pcc->excp_model = POWERPC_EXCP_40x;
PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000007D00DULL;
pcc->mmu_model = POWERPC_MMU_REAL;
pcc->excp_model = POWERPC_EXCP_40x;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_40x_EXCP;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000007D00DULL;
pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
pcc->excp_model = POWERPC_EXCP_40x;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006E630ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
pcc->excp_model = POWERPC_EXCP_40x;
PPC_MEM_TLBSYNC | PPC_MFTB |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006FF30ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE;
pcc->excp_model = POWERPC_EXCP_BOOKE;
PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006FF30ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE;
pcc->excp_model = POWERPC_EXCP_BOOKE;
PPC_MEM_TLBSYNC | PPC_MFTB |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006FF30ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE;
pcc->excp_model = POWERPC_EXCP_BOOKE;
PPC_MEM_TLBSYNC | PPC_MFTB |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006FF30ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE;
pcc->excp_model = POWERPC_EXCP_BOOKE;
PPC_MEM_TLBSYNC | PPC_TLBIVA |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006FF30ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE;
pcc->excp_model = POWERPC_EXCP_BOOKE;
PPC_MEM_TLBSYNC | PPC_TLBIVA |
PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
PPC_440_SPEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006FF30ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE;
pcc->excp_model = POWERPC_EXCP_BOOKE;
PPC_MEM_EIEIO | PPC_MEM_SYNC |
PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
PPC_MFTB;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000001FF43ULL;
pcc->mmu_model = POWERPC_MMU_REAL;
pcc->excp_model = POWERPC_EXCP_603;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
PPC_MEM_EIEIO | PPC_MEM_SYNC |
PPC_CACHE_ICBI | PPC_MFTB;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000001F673ULL;
pcc->mmu_model = POWERPC_MMU_MPC8xx;
pcc->excp_model = POWERPC_EXCP_603;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000006FFF2ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
pcc->excp_model = POWERPC_EXCP_G2;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000007FFF3ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
pcc->excp_model = POWERPC_EXCP_G2;
PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
PPC_MEM_TLBSYNC | PPC_TLBIVAX |
PPC_BOOKE;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000606FF30ULL;
pcc->mmu_model = POWERPC_MMU_BOOKE206;
pcc->excp_model = POWERPC_EXCP_BOOKE;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000007FFF3ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
pcc->excp_model = POWERPC_EXCP_603;
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000000FD70ULL;
pcc->mmu_model = POWERPC_MMU_601;
#if defined(CONFIG_SOFTMMU)
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000000FD70ULL;
pcc->mmu_model = POWERPC_MMU_601;
#if defined(CONFIG_SOFTMMU)
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_602_SPEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x0000000000C7FF73ULL;
/* XXX: 602 MMU is quite specific. Should add a special case */
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000007FF73ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
pcc->excp_model = POWERPC_EXCP_603;
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
- spr_register(env, SPR_IABR, "IABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
gen_low_BATs(env);
gen_6xx_7xx_soft_tlb(env, 64, 2);
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000007FF73ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
pcc->excp_model = POWERPC_EXCP_603E;
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Time base */
gen_tbl(env);
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Time base */
gen_tbl(env);
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Time base */
gen_tbl(env);
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Time base */
gen_tbl(env);
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented (XXX: different from 750fx) */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Time base */
gen_tbl(env);
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
pcc->excp_model = POWERPC_EXCP_7x5;
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* XXX : not implemented */
spr_register(env, SPR_L2PMCR, "L2PMCR",
PPC_MEM_SYNC | PPC_MEM_EIEIO |
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
PPC_SEGMENT | PPC_EXTERN;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000005FF77ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
pcc->excp_model = POWERPC_EXCP_7x5;
PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
PPC_MEM_TLBIA |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_32B;
#if defined(CONFIG_SOFTMMU)
PPC_MEM_TLBIA | PPC_74xx_TLB |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
pcc->excp_model = POWERPC_EXCP_74xx;
PPC_MEM_TLBIA | PPC_74xx_TLB |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
pcc->excp_model = POWERPC_EXCP_74xx;
PPC_MEM_TLBIA | PPC_74xx_TLB |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
pcc->excp_model = POWERPC_EXCP_74xx;
PPC_MEM_TLBIA | PPC_74xx_TLB |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
pcc->excp_model = POWERPC_EXCP_74xx;
PPC_MEM_TLBIA | PPC_74xx_TLB |
PPC_SEGMENT | PPC_EXTERN |
PPC_ALTIVEC;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x000000000205FF77ULL;
pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
pcc->excp_model = POWERPC_EXCP_74xx;
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Memory management */
/* XXX: not correct */
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x900000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Memory management */
/* XXX: not correct */
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Memory management */
/* XXX: not correct */
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
#if defined(CONFIG_SOFTMMU)
/* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, NULL,
0x00000000);
/* Memory management */
/* XXX: not correct */
PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI;
- pcc->insns_flags2 = PPC_NONE;
pcc->msr_mask = 0x900000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_64B;
#if defined(CONFIG_SOFTMMU)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DSCR, 0x00000000);
+ spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_MMCRA, 0x00000000);
+ spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC5, 0x00000000);
+ spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PMC6, 0x00000000);
#endif /* !CONFIG_USER_ONLY */
/* Memory management */
/* XXX : not implemented */
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
+ spr_register(env, SPR_PPR, "PPR",
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
#if !defined(CONFIG_USER_ONLY)
env->slb_nr = 32;
#endif
PPC_64B | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
- pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX;
+ pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205;
pcc->msr_mask = 0x800000000204FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
{
opc_handler_t **tmp;
- tmp = malloc(0x20 * sizeof(opc_handler_t));
+ tmp = g_malloc(0x20 * sizeof(opc_handler_t));
fill_new_table(tmp, 0x20);
table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
34, "power-spe.xml", 0);
}
- qemu_init_vcpu(env);
-
pcc->parent_realize(dev, errp);
#if defined(PPC_DUMP_CPU)
#endif
}
+static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(dev);
+ CPUPPCState *env = &cpu->env;
+ int i;
+
+ for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
+ if (env->opcodes[i] != &invalid_handler) {
+ g_free(env->opcodes[i]);
+ }
+ }
+}
+
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
{
ObjectClass *oc = (ObjectClass *)a;
#include <ctype.h>
+static ObjectClass *ppc_cpu_class_by_name(const char *name);
+
+static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
+{
+ ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
+
+ /* Cache target class lookups in the alias table */
+ if (!alias->oc) {
+ alias->oc = ppc_cpu_class_by_name(alias->model);
+ if (!alias->oc) {
+ /* Fast check for non-existing aliases */
+ alias->oc = invalid_class;
+ }
+ }
+
+ if (alias->oc == invalid_class) {
+ return NULL;
+ } else {
+ return alias->oc;
+ }
+}
+
static ObjectClass *ppc_cpu_class_by_name(const char *name)
{
GSList *list, *item;
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
- return ppc_cpu_class_by_name(ppc_cpu_aliases[i].model);
+ return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
}
}
(*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
name, pcc->pvr);
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
- const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
- ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
+ PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
+ ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
if (alias_oc != oc) {
continue;
g_slist_free(list);
for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
- const PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
+ PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
ObjectClass *oc;
CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
- oc = ppc_cpu_class_by_name(alias->model);
+ oc = ppc_cpu_class_by_alias(alias);
if (oc == NULL) {
continue;
}
pcc->parent_realize = dc->realize;
dc->realize = ppc_cpu_realizefn;
+ dc->unrealize = ppc_cpu_unrealizefn;
pcc->parent_reset = cc->reset;
cc->reset = ppc_cpu_reset;
cc->class_by_name = ppc_cpu_class_by_name;
cc->do_interrupt = ppc_cpu_do_interrupt;
+ cc->dump_state = ppc_cpu_dump_state;
+ cc->dump_statistics = ppc_cpu_dump_statistics;
}
static const TypeInfo ppc_cpu_type_info = {