Merge remote-tracking branch 'stefanha/block' into staging

[qemu.git] / target-sh4 / translate.c

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 6305db80f7e5a947a418ce0305f7429c19f7f620..260aaab5596194b638c7c67e9aa6aa06b65c1214 100644 (file)
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -18,11 +18,10 @@
  */
 
 #define DEBUG_DISAS
-#define SH4_DEBUG_DISAS
 //#define SH4_SINGLE_STEP
 
 #include "cpu.h"
-#include "disas.h"
+#include "disas/disas.h"
 #include "tcg-op.h"
 
 #include "helper.h"
@@ -32,8 +31,6 @@
 typedef struct DisasContext {
     struct TranslationBlock *tb;
     target_ulong pc;
-    uint32_t sr;
-    uint32_t fpscr;
     uint16_t opcode;
     uint32_t flags;
     int bstate;
@@ -47,7 +44,7 @@ typedef struct DisasContext {
 #if defined(CONFIG_USER_ONLY)
 #define IS_USER(ctx) 1
 #else
-#define IS_USER(ctx) (!(ctx->sr & SR_MD))
+#define IS_USER(ctx) (!(ctx->flags & SR_MD))
 #endif
 
 enum {
@@ -72,7 +69,7 @@ static TCGv cpu_flags, cpu_delayed_pc;
 
 static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
 
-#include "gen-icount.h"
+#include "exec/gen-icount.h"
 
 static void sh4_translate_init(void)
 {
@@ -413,15 +410,15 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
 #define B11_8 ((ctx->opcode >> 8) & 0xf)
 #define B15_12 ((ctx->opcode >> 12) & 0xf)
 
-#define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
-               (cpu_gregs[x + 16]) : (cpu_gregs[x]))
+#define REG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) == (SR_MD | SR_RB) \
+                ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 
-#define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
+#define ALTREG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) != (SR_MD | SR_RB)\
                ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
 
-#define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
+#define FREG(x) (ctx->flags & FPSCR_FR ? (x) ^ 0x10 : (x))
 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
+#define XREG(x) (ctx->flags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
 #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
 
 #define CHECK_NOT_DELAY_SLOT \
@@ -537,7 +534,7 @@ static void _decode_opc(DisasContext * ctx)
        ctx->bstate = BS_STOP;
        return;
     case 0xf3fd:               /* fschg */
-       tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
+        tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
        ctx->bstate = BS_STOP;
        return;
     case 0x0009:               /* nop */
@@ -1080,7 +1077,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_SZ) {
+        if (ctx->flags & FPSCR_SZ) {
            TCGv_i64 fp = tcg_temp_new_i64();
            gen_load_fpr64(fp, XREG(B7_4));
            gen_store_fpr64(fp, XREG(B11_8));
@@ -1091,7 +1088,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_SZ) {
+        if (ctx->flags & FPSCR_SZ) {
            TCGv addr_hi = tcg_temp_new();
            int fr = XREG(B7_4);
            tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
@@ -1104,7 +1101,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_SZ) {
+        if (ctx->flags & FPSCR_SZ) {
            TCGv addr_hi = tcg_temp_new();
            int fr = XREG(B11_8);
            tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
@@ -1117,7 +1114,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_SZ) {
+        if (ctx->flags & FPSCR_SZ) {
            TCGv addr_hi = tcg_temp_new();
            int fr = XREG(B11_8);
            tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
@@ -1132,7 +1129,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_SZ) {
+        if (ctx->flags & FPSCR_SZ) {
            TCGv addr = tcg_temp_new_i32();
            int fr = XREG(B7_4);
            tcg_gen_subi_i32(addr, REG(B11_8), 4);
@@ -1155,7 +1152,7 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new_i32();
            tcg_gen_add_i32(addr, REG(B7_4), REG(0));
-           if (ctx->fpscr & FPSCR_SZ) {
+            if (ctx->flags & FPSCR_SZ) {
                int fr = XREG(B11_8);
                tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
                tcg_gen_addi_i32(addr, addr, 4);
@@ -1171,7 +1168,7 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_add_i32(addr, REG(B11_8), REG(0));
-           if (ctx->fpscr & FPSCR_SZ) {
+            if (ctx->flags & FPSCR_SZ) {
                int fr = XREG(B7_4);
                tcg_gen_qemu_ld32u(cpu_fregs[fr  ], addr, ctx->memidx);
                tcg_gen_addi_i32(addr, addr, 4);
@@ -1190,7 +1187,7 @@ static void _decode_opc(DisasContext * ctx)
     case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
        {
            CHECK_FPU_ENABLED
-           if (ctx->fpscr & FPSCR_PR) {
+            if (ctx->flags & FPSCR_PR) {
                 TCGv_i64 fp0, fp1;
 
                if (ctx->opcode & 0x0110)
@@ -1259,7 +1256,7 @@ static void _decode_opc(DisasContext * ctx)
     case 0xf00e: /* fmac FR0,RM,Rn */
         {
             CHECK_FPU_ENABLED
-            if (ctx->fpscr & FPSCR_PR) {
+            if (ctx->flags & FPSCR_PR) {
                 break; /* illegal instruction */
             } else {
                 gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
@@ -1789,7 +1786,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_PR) {
+        if (ctx->flags & FPSCR_PR) {
            TCGv_i64 fp;
            if (ctx->opcode & 0x0100)
                break; /* illegal instruction */
@@ -1804,7 +1801,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_PR) {
+        if (ctx->flags & FPSCR_PR) {
            TCGv_i64 fp;
            if (ctx->opcode & 0x0100)
                break; /* illegal instruction */
@@ -1825,7 +1822,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf05d: /* fabs FRn/DRn */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_PR) {
+        if (ctx->flags & FPSCR_PR) {
            if (ctx->opcode & 0x0100)
                break; /* illegal instruction */
            TCGv_i64 fp = tcg_temp_new_i64();
@@ -1839,7 +1836,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf06d: /* fsqrt FRn */
        CHECK_FPU_ENABLED
-       if (ctx->fpscr & FPSCR_PR) {
+        if (ctx->flags & FPSCR_PR) {
            if (ctx->opcode & 0x0100)
                break; /* illegal instruction */
            TCGv_i64 fp = tcg_temp_new_i64();
@@ -1857,13 +1854,13 @@ static void _decode_opc(DisasContext * ctx)
        break;
     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
        CHECK_FPU_ENABLED
-       if (!(ctx->fpscr & FPSCR_PR)) {
+        if (!(ctx->flags & FPSCR_PR)) {
            tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
        }
        return;
     case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
        CHECK_FPU_ENABLED
-       if (!(ctx->fpscr & FPSCR_PR)) {
+        if (!(ctx->flags & FPSCR_PR)) {
            tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
        }
        return;
@@ -1887,7 +1884,7 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0xf0ed: /* fipr FVm,FVn */
         CHECK_FPU_ENABLED
-        if ((ctx->fpscr & FPSCR_PR) == 0) {
+        if ((ctx->flags & FPSCR_PR) == 0) {
             TCGv m, n;
             m = tcg_const_i32((ctx->opcode >> 8) & 3);
             n = tcg_const_i32((ctx->opcode >> 10) & 3);
@@ -1900,7 +1897,7 @@ static void _decode_opc(DisasContext * ctx)
     case 0xf0fd: /* ftrv XMTRX,FVn */
         CHECK_FPU_ENABLED
         if ((ctx->opcode & 0x0300) == 0x0100 &&
-            (ctx->fpscr & FPSCR_PR) == 0) {
+            (ctx->flags & FPSCR_PR) == 0) {
             TCGv n;
             n = tcg_const_i32((ctx->opcode >> 10) & 3);
             gen_helper_ftrv(cpu_env, n);
@@ -1927,7 +1924,7 @@ static void decode_opc(DisasContext * ctx)
 {
     uint32_t old_flags = ctx->flags;
 
-    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+    if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
         tcg_gen_debug_insn_start(ctx->pc);
     }
 
@@ -1970,20 +1967,18 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
     int max_insns;
 
     pc_start = tb->pc;
-    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
+    gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
     ctx.pc = pc_start;
     ctx.flags = (uint32_t)tb->flags;
     ctx.bstate = BS_NONE;
-    ctx.sr = env->sr;
-    ctx.fpscr = env->fpscr;
-    ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0;
+    ctx.memidx = (ctx.flags & SR_MD) == 0 ? 1 : 0;
     /* We don't know if the delayed pc came from a dynamic or static branch,
        so assume it is a dynamic branch.  */
     ctx.delayed_pc = -1; /* use delayed pc from env pointer */
     ctx.tb = tb;
     ctx.singlestep_enabled = env->singlestep_enabled;
     ctx.features = env->features;
-    ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA);
+    ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
 
     ii = -1;
     num_insns = 0;
@@ -1991,7 +1986,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
     if (max_insns == 0)
         max_insns = CF_COUNT_MASK;
     gen_icount_start();
-    while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
+    while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) {
         if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
             QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
                 if (ctx.pc == bp->pc) {
@@ -2004,16 +1999,16 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
            }
        }
         if (search_pc) {
-            i = gen_opc_ptr - gen_opc_buf;
+            i = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
             if (ii < i) {
                 ii++;
                 while (ii < i)
-                    gen_opc_instr_start[ii++] = 0;
+                    tcg_ctx.gen_opc_instr_start[ii++] = 0;
             }
-            gen_opc_pc[ii] = ctx.pc;
+            tcg_ctx.gen_opc_pc[ii] = ctx.pc;
             gen_opc_hflags[ii] = ctx.flags;
-            gen_opc_instr_start[ii] = 1;
-            gen_opc_icount[ii] = num_insns;
+            tcg_ctx.gen_opc_instr_start[ii] = 1;
+            tcg_ctx.gen_opc_icount[ii] = num_insns;
         }
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
             gen_io_start();
@@ -2061,24 +2056,21 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
     }
 
     gen_icount_end(tb, num_insns);
-    *gen_opc_ptr = INDEX_op_end;
+    *tcg_ctx.gen_opc_ptr = INDEX_op_end;
     if (search_pc) {
-        i = gen_opc_ptr - gen_opc_buf;
+        i = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
         ii++;
         while (ii <= i)
-            gen_opc_instr_start[ii++] = 0;
+            tcg_ctx.gen_opc_instr_start[ii++] = 0;
     } else {
         tb->size = ctx.pc - pc_start;
         tb->icount = num_insns;
     }
 
 #ifdef DEBUG_DISAS
-#ifdef SH4_DEBUG_DISAS
-    qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
-#endif
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
        qemu_log("IN:\n");      /* , lookup_symbol(pc_start)); */
-       log_target_disas(pc_start, ctx.pc - pc_start, 0);
+        log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
        qemu_log("\n");
     }
 #endif
@@ -2096,6 +2088,6 @@ void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb)
 
 void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos)
 {
-    env->pc = gen_opc_pc[pc_pos];
+    env->pc = tcg_ctx.gen_opc_pc[pc_pos];
     env->flags = gen_opc_hflags[pc_pos];
 }