X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;ds=sidebyside;f=OvmfPkg%2FPlatformPei%2FPlatform.c;h=1126c6529ae2aeea4129379599b25bc39d474a95;hb=da372167684822ddd0cce01e5282502da28538a4;hp=ce149e4f979e2c6589fa383ebc2b4232e9df99dc;hpb=931a0c74ed405a9b61afaa7ce1796f3e656d90b9;p=mirror_edk2.git
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index ce149e4f97..1126c6529a 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -1,7 +1,7 @@
/**@file
Platform PEI driver
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
Copyright (c) 2011, Andrei Warkentin
This program and the accompanying materials
@@ -30,10 +30,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include "Platform.h"
#include "Cmos.h"
@@ -59,6 +61,11 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {
};
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+BOOLEAN mS3Supported = FALSE;
+
+
VOID
AddIoMemoryBaseSizeHob (
EFI_PHYSICAL_ADDRESS MemoryBase,
@@ -163,10 +170,9 @@ AddUntestedMemoryRangeHob (
AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-
VOID
MemMapInitialization (
- EFI_PHYSICAL_ADDRESS TopOfMemory
+ VOID
)
{
//
@@ -194,29 +200,41 @@ MemMapInitialization (
//
AddIoMemoryRangeHob (0x0A0000, BASE_1MB);
- //
- // address purpose size
- // ------------ -------- -------------------------
- // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
- // 0xFC000000 gap 44 MB
- // 0xFEC00000 IO-APIC 4 KB
- // 0xFEC01000 gap 1020 KB
- // 0xFED00000 HPET 1 KB
- // 0xFED00400 gap 1023 KB
- // 0xFEE00000 LAPIC 1 MB
- //
- AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000);
- AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
- AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
- AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
+ if (!mXen) {
+ UINT32 TopOfLowRam;
+ TopOfLowRam = GetSystemMemorySizeBelow4gb ();
+
+ //
+ // address purpose size
+ // ------------ -------- -------------------------
+ // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
+ // 0xFC000000 gap 44 MB
+ // 0xFEC00000 IO-APIC 4 KB
+ // 0xFEC01000 gap 1020 KB
+ // 0xFED00000 HPET 1 KB
+ // 0xFED00400 gap 1023 KB
+ // 0xFEE00000 LAPIC 1 MB
+ //
+ AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
+ BASE_2GB : TopOfLowRam, 0xFC000000);
+ AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
+ AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
+ AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
+ }
}
VOID
MiscInitialization (
- BOOLEAN Xen
+ VOID
)
{
+ UINT16 HostBridgeDevId;
+ UINTN PmCmd;
+ UINTN Pmba;
+ UINTN AcpiCtlReg;
+ UINT8 AcpiEnBit;
+
//
// Disable A20 Mask
//
@@ -227,40 +245,68 @@ MiscInitialization (
//
BuildCpuHob (36, 16);
- if (!Xen) {
+ //
+ // Query Host Bridge DID to determine platform type and save to PCD
+ //
+ HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+ switch (HostBridgeDevId) {
+ case INTEL_82441_DEVICE_ID:
+ PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
+ Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+ AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+ AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
+ break;
+ case INTEL_Q35_MCH_DEVICE_ID:
+ PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
+ Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+ AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
+ AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
+ break;
+ default:
+ DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
+ __FUNCTION__, HostBridgeDevId));
+ ASSERT (FALSE);
+ return;
+ }
+ PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId);
+
+ //
+ // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
+ // has been configured (e.g., by Xen) and skip the setup here.
+ // This matches the logic in AcpiTimerLibConstructor ().
+ //
+ if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
//
- // The PEI phase should be exited with fully accessibe PIIX4 IO space:
+ // The PEI phase should be exited with fully accessibe ACPI PM IO space:
// 1. set PMBA
//
- PciAndThenOr32 (
- PCI_LIB_ADDRESS (0, 1, 3, 0x40),
- (UINT32) ~0xFFC0,
- PcdGet16 (PcdAcpiPmBaseAddress)
- );
+ PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
//
// 2. set PCICMD/IOSE
//
- PciOr8 (
- PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),
- EFI_PCI_COMMAND_IO_SPACE
- );
+ PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
//
- // 3. set PMREGMISC/PMIOSE
+ // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
//
- PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
+ PciOr8 (AcpiCtlReg, AcpiEnBit);
}
}
VOID
BootModeInitialization (
+ VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);
+ if (CmosRead8 (0xF) == 0xFE) {
+ mBootMode = BOOT_ON_S3_RESUME;
+ }
+
+ Status = PeiServicesSetBootMode (mBootMode);
ASSERT_EFI_ERROR (Status);
Status = PeiServicesInstallPpi (mPpiBootMode);
@@ -282,8 +328,9 @@ ReserveEmuVariableNvStore (
//
VariableStore =
(EFI_PHYSICAL_ADDRESS)(UINTN)
- AllocateRuntimePool (
- 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)
+ AllocateAlignedRuntimePages (
+ EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),
+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)
);
DEBUG ((EFI_D_INFO,
"Reserved variable store memory: 0x%lX; size: %dkb\n",
@@ -331,28 +378,37 @@ InitializePlatform (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS TopOfMemory;
- BOOLEAN Xen;
-
DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));
DebugDumpCmos ();
- TopOfMemory = MemDetect ();
+ XenDetect ();
- Status = InitializeXen ();
- Xen = EFI_ERROR (Status) ? FALSE : TRUE;
+ if (QemuFwCfgS3Enabled ()) {
+ DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
+ mS3Supported = TRUE;
+ }
- ReserveEmuVariableNvStore ();
+ BootModeInitialization ();
+
+ PublishPeiMemory ();
- PeiFvInitialization ();
+ InitializeRamRegions ();
- MemMapInitialization (TopOfMemory);
+ if (mXen) {
+ DEBUG ((EFI_D_INFO, "Xen was detected\n"));
+ InitializeXen ();
+ }
- MiscInitialization (Xen);
+ if (mBootMode != BOOT_ON_S3_RESUME) {
+ ReserveEmuVariableNvStore ();
- BootModeInitialization ();
+ PeiFvInitialization ();
+
+ MemMapInitialization ();
+ }
+
+ MiscInitialization ();
return EFI_SUCCESS;
}