X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FArmPkg.dec;h=75c238aa1e3d580318b941dc4d2eb7cbcb537cc2;hb=08c6239d03876ca4df618a499d674d8b04545976;hp=05bc1dcd6d613c042c01f304b6ee13aac5a5de9e;hpb=f8d7d6e151e9377412bd368cf8901ac21d6edb36;p=mirror_edk2.git diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 05bc1dcd6d..75c238aa1e 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -2,7 +2,7 @@ # ARM processor package. # # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. +# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -38,6 +38,7 @@ UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h + ArmGicArchLib|Include/Library/ArmGicArchLib.h [Guids.common] gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } } @@ -59,7 +60,7 @@ # On ARM Architecture with the Security Extension, the address for the # Vector Table can be mapped anywhere in the memory map. It means we can # point the Exception Vector Table to its location in CpuDxe. - # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress) + # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress) gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before # it has been configured by the CPU DXE @@ -69,6 +70,15 @@ # Linux (instead of PSCI) gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033 + # Define if the GICv3 controller should use the GICv2 legacy + gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 + +[PcdsFeatureFlag.ARM] + # Whether to map normal memory as non-shareable. FALSE is the safe choice, but + # TRUE may be appropriate to fix performance problems if you don't care about + # hardware coherency (i.e., no virtualization or cache coherent DMA) + gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043 + [PcdsFixedAtBuild.common] gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 @@ -77,26 +87,20 @@ gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024 gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002 - gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003 - gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004 + # This PCD will free the unallocated buffers if their size reach this threshold. + # We set the default value to 512MB. + gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003 + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 # # ARM Secure Firmware PCDs # - gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015 + gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 - gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F + gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 - # - # ARM Normal (or Non Secure) Firmware PCDs - # - gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B - gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C - gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D - gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E - # # ARM Hypervisor Firmware PCDs # @@ -118,12 +122,20 @@ # # BdsLib # - gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F # Maximum file size for TFTP servers that do not support 'tsize' extension gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000 + # + # ARM Normal (or Non Secure) Firmware PCDs + # + gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C + gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E + +[PcdsFixedAtBuild.common, PcdsPatchableInModule.common] + gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B + gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D [PcdsFixedAtBuild.ARM] # @@ -204,16 +216,18 @@ # -# These PCDs are also defined as 'PcdsDynamic' to be redefined when using UEFI in a -# context of virtual machine. +# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be +# redefined when using UEFI in a context of virtual machine. # -[PcdsFixedAtBuild.common, PcdsDynamic.common] +[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common] + # System Memory (DRAM): These PCDs define the region of in-built system memory # Some platforms can get DRAM extensions, these additional regions will be declared # to UEFI by ArmPlatformLib gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A +[PcdsFixedAtBuild.common, PcdsDynamic.common] # # ARM Architectural Timer # @@ -225,9 +239,81 @@ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041 + # + # ARM Generic Watchdog + # + + gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007 + gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008 + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009 + # # ARM Generic Interrupt Controller # gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C + # Base address for the GIC Redistributor region that contains the boot CPU + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 + + # + # Bases, sizes and translation offsets of IO and MMIO spaces, respectively. + # Note that "IO" is just another MMIO range that simulates IO space; there + # are no special instructions to access it. + # + # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are + # specific to their containing address spaces. In order to get the physical + # address for the CPU, for a given access, the respective translation value + # has to be added. + # + # The translations always have to be initialized like this, using UINT64: + # + # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space + # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space + # + # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase; + # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base; + # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base; + # + # because (a) the target address space (ie. the cpu-physical space) is + # 64-bit, and (b) the translation values are meant as offsets for *modular* + # arithmetic. + # + # Accordingly, the translation itself needs to be implemented as: + # + # UINT64 UntranslatedIoAddress; // input parameter + # UINT32 UntranslatedMmio32Address; // input parameter + # UINT64 UntranslatedMmio64Address; // input parameter + # + # UINT64 TranslatedIoAddress; // output parameter + # UINT64 TranslatedMmio32Address; // output parameter + # UINT64 TranslatedMmio64Address; // output parameter + # + # TranslatedIoAddress = UntranslatedIoAddress + + # PcdPciIoTranslation; + # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address + + # PcdPciMmio32Translation; + # TranslatedMmio64Address = UntranslatedMmio64Address + + # PcdPciMmio64Translation; + # + # The modular arithmetic performed in UINT64 ensures that the translation + # works correctly regardless of the relation between IoCpuBase and + # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and + # PcdPciMmio64Base. + # + gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050 + gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051 + gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052 + gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053 + gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054 + gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055 + gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056 + gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057 + gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058 + + # + # Inclusive range of allowed PCI buses. + # + gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059 + gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A