X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FArmPkg.dec;h=87dbd11b867fa9097255175758a33e29d15dbbc9;hb=b6242db90a340a934f4ab2313df76b44c9b1dcb0;hp=c12de9481beebc97b03dbb169ee2361bcec4aa63;hpb=9207c5d75871fed9f98ee6548e9d420e4d11f340;p=mirror_edk2.git

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index c12de9481b..87dbd11b86 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -2,7 +2,7 @@
 # ARM processor package.
 #
 # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
-# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.
 #
 #    This program and the accompanying materials
 #    are licensed and made available under the terms and conditions of the BSD License
@@ -38,7 +38,7 @@
   UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
   DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
   ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
-  
+
 [Guids.common]
   gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
 
@@ -64,7 +64,14 @@
   # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
   # it has been configured by the CPU DXE
   gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
-  
+
+  # Define if the spin-table mechanism is used by the secondary cores when booting
+  # Linux (instead of PSCI)
+  gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
+
+  # Define if the GICv3 controller should use the GICv2 legacy
+  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
+
 [PcdsFixedAtBuild.common]
   gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
 
@@ -73,39 +80,65 @@
   gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
 
   gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
+  # This PCD will free the unallocated buffers if their size reach this threshold.
+  # We set the default value to 512MB.
+  gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000043
   gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
   gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
-  
-  #
-  # ARM PL390 General Interrupt Controller
-  #
-  gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
-  gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023
 
   #
   # ARM Secure Firmware PCDs
   #
-  gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015
+  gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015
   gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016
-  gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F
+  gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F
   gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030
 
+  #
+  # ARM Hypervisor Firmware PCDs
+  #
+  gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A
+  gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
+  gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
+  gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
+
+  # Use ClusterId + CoreId to identify the PrimaryCore
+  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
+  # The Primary Core is ClusterId[0] & CoreId[0]
+  gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
+
+  #
+  # ARM L2x0 PCDs
+  #
+  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
+
+  #
+  # BdsLib
+  #
+  gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
+  # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
+  gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
+  # Maximum file size for TFTP servers that do not support 'tsize' extension
+  gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000
+
   #
   # ARM Normal (or Non Secure) Firmware PCDs
   #
-  gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B
   gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
-  gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D
   gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
-  
+
+[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
+  gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
+  gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
+
+[PcdsFixedAtBuild.ARM]
   #
   # ARM Security Extension
   #
-  
+
   # Secure Configuration Register
-  # - BIT0 : NS - Non Secure bit 
+  # - BIT0 : NS - Non Secure bit
   # - BIT1 : IRQ Handler
   # - BIT2 : FIQ Handler
   # - BIT3 : EA - External Abort
@@ -117,52 +150,103 @@
   # - BIT9 : SIF - Secure Instruction Fetch
   # 0x31 = NS | EA | FW
   gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
-  
+
+  # By default we do not do a transition to non-secure mode
+  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
+
+  # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
+  gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
+
+  # If the fixed FDT address is not available, then it should be loaded below the kernel.
+  # The recommendation from the Linux kernel is to have the FDT below 16KB.
+  # (see the kernel doc: Documentation/arm/Booting)
+  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
+  # The FDT blob must be loaded at a 64bit aligned address.
+  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
+
   # Non Secure Access Control Register
   # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
-  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 
+  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
   # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
   # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
   # 0xC00 = cp10 | cp11
   gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
-  
-  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
+
+[PcdsFixedAtBuild.AARCH64]
+  #
+  # AArch64 Security Extension
+  #
+
+  # Secure Configuration Register
+  # - BIT0 : NS - Non Secure bit
+  # - BIT1 : IRQ Handler
+  # - BIT2 : FIQ Handler
+  # - BIT3 : EA - External Abort
+  # - BIT4 : FW - F bit writable
+  # - BIT5 : AW - A bit writable
+  # - BIT6 : nET - Not Early Termination
+  # - BIT7 : SCD - Secure Monitor Call Disable
+  # - BIT8 : HCE - Hyp Call enable
+  # - BIT9 : SIF - Secure Instruction Fetch
+  # - BIT10: RW -  Register width control for lower exception levels
+  # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
+  # - BIT12: TWI - Trap WFI
+  # - BIT13: TWE - Trap WFE
+  # 0x501 = NS | HCE | RW
+  gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
+
+  # By default we do transition to EL2 non-secure mode with Stack for EL2.
+  #        Mode Description              Bits
+  # NS EL2 SP2 all interrupts disabled =  0x3c9
+  # NS EL1 SP1 all interrupts disabled =  0x3c5
+  # Other modes include using SP0 or switching to Aarch32, but these are
+  # not currently supported.
+  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
+  # If the fixed FDT address is not available, then it should be loaded above the kernel.
+  # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
+  # (see the kernel doc: Documentation/arm64/booting.txt)
+  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
+  # The FDT blob must be loaded at a 2MB aligned address.
+  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
+
+
+#
+# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be
+# redefined when using UEFI in a context of virtual machine.
+#
+[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
 
   # System Memory (DRAM): These PCDs define the region of in-built system memory
   # Some platforms can get DRAM extensions, these additional regions will be declared
-  # to UEFI by ArmPLatformPlib   
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A
-
-  # Use ClusterId + CoreId to identify the PrimaryCore
-  gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
-  # The Primary Core is ClusterId[0] & CoreId[0] 
-  gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
+  # to UEFI by ArmPlatformLib
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 
+[PcdsFixedAtBuild.common, PcdsDynamic.common]
   #
-  # ARM L2x0 PCDs
-  #
-  gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
-  
+  # ARM Architectural Timer
   #
-  # ARM PL390 General Interrupt Controller
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
+
+  # ARM Architectural Timer Interrupt(GIC PPI) numbers
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041
+
   #
-  gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C
-  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D
-  
-  # 
-  # BdsLib
+  # ARM Generic Watchdog
   #
-  gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
-  # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
-  gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
-  # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
-  gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
+
+  gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007
+  gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008
+  gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
 
   #
-  # ARM Architectural Timer
+  # ARM Generic Interrupt Controller
   #
-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034
-  # ARM Architectural Timer Interrupt(GIC PPI) number
-  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035  
-  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
+  # Base address for the GIC Redistributor region that contains the boot CPU
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
+  gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025