X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FArmPkg.dec;h=cfb6fe602485aa7bc3e91f48caf5bbbbe9b7a761;hb=31b16384688df9ce0e8f59021fd667e47d7d3972;hp=87dbd11b867fa9097255175758a33e29d15dbbc9;hpb=523b5266b775f18e2aa364cee17bfe6501707ac3;p=mirror_edk2.git
diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index 87dbd11b86..cfb6fe6024 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -2,15 +2,10 @@
# ARM processor package.
#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2021, ARM Limited. All rights reserved.
+# Copyright (c) 2021, Ampere Computing LLC. All rights reserved.
#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
#
#**/
@@ -33,11 +28,69 @@
Include # Root include for the package
[LibraryClasses.common]
+ ## @libraryclass Convert Arm instructions to a human readable format.
+ #
+ ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
+
+ ## @libraryclass Provides an interface to Arm generic counters.
+ #
+ ArmGenericTimerCounterLib|Include/Library/ArmGenericTimerCounterLib.h
+
+ ## @libraryclass Provides an interface to initialize a
+ # Generic Interrupt Controller (GIC).
+ #
+ ArmGicArchLib|Include/Library/ArmGicArchLib.h
+
+ ## @libraryclass Provides a Generic Interrupt Controller (GIC)
+ # configuration interface.
+ #
+ ArmGicLib|Include/Library/ArmGicLib.h
+
+ ## @libraryclass Provides a HyperVisor Call (HVC) interface.
+ #
+ ArmHvcLib|Include/Library/ArmHvcLib.h
+
+ ## @libraryclass Provides an interface to Arm registers.
+ #
ArmLib|Include/Library/ArmLib.h
- SemihostLib|Include/Library/Semihosting.h
- UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h
+
+ ## @libraryclass Provides a Mmu interface.
+ #
+ ArmMmuLib|Include/Library/ArmMmuLib.h
+
+ ## @libraryclass Provides a Mailbox Transport Layer (MTL) interface
+ # for the System Control and Management Interface (SCMI).
+ #
+ ArmMtlLib|Include/Library/ArmMtlLib.h
+
+ ## @libraryclass Provides a System Monitor Call (SMC) interface.
+ #
+ ArmSmcLib|Include/Library/ArmSmcLib.h
+
+ ## @libraryclass Provides a SuperVisor Call (SVC) interface.
+ #
+ ArmSvcLib|Include/Library/ArmSvcLib.h
+
+ ## @libraryclass Provides a default exception handler.
+ #
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h
- ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h
+
+ ## @libraryclass Provides an interface to query miscellaneous OEM
+ # information.
+ #
+ OemMiscLib|Include/Library/OemMiscLib.h
+
+ ## @libraryclass Provides an OpTee interface.
+ #
+ OpteeLib|Include/Library/OpteeLib.h
+
+ ## @libraryclass Provides a semihosting interface.
+ #
+ SemihostLib|Include/Library/SemihostLib.h
+
+ ## @libraryclass Provides an interface for a StandaloneMm Mmu.
+ #
+ StandaloneMmMmuLib|Include/Library/StandaloneMmMmuLib.h
[Guids.common]
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }
@@ -46,32 +99,54 @@
# Include/Guid/ArmMpCoreInfo.h
gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
+ gArmMmuReplaceLiveTranslationEntryFuncGuid = { 0xa8b50ff3, 0x08ec, 0x4dd3, {0xbf, 0x04, 0x28, 0xbf, 0x71, 0x75, 0xc7, 0x4a} }
+
+[Protocols.common]
+ ## Arm System Control and Management Interface(SCMI) Base protocol
+ ## ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h
+ gArmScmiBaseProtocolGuid = { 0xd7e5abe9, 0x33ab, 0x418e, { 0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f } }
+
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol
+ ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h
+ gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } }
+ gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } }
+
+ ## Arm System Control and Management Interface(SCMI) Clock management protocol
+ ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h
+ gArmScmiPerformanceProtocolGuid = { 0x9b8ba84, 0x3dd3, 0x49a6, { 0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad } }
+
[Ppis]
## Include/Ppi/ArmMpCoreInfo.h
gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }
-[Protocols.common]
- gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }
-
[PcdsFeatureFlag.common]
gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001
# On ARM Architecture with the Security Extension, the address for the
# Vector Table can be mapped anywhere in the memory map. It means we can
# point the Exception Vector Table to its location in CpuDxe.
- # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress)
+ # By default we copy the Vector Table at PcdGet64(PcdCpuVectorBaseAddress)
gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022
# Set this PCD to TRUE if the Exception Vector is changed to add debugger support before
# it has been configured by the CPU DXE
gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032
- # Define if the spin-table mechanism is used by the secondary cores when booting
- # Linux (instead of PSCI)
- gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033
-
# Define if the GICv3 controller should use the GICv2 legacy
gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042
+[PcdsFeatureFlag.ARM]
+ # Whether to map normal memory as non-shareable. FALSE is the safe choice, but
+ # TRUE may be appropriate to fix performance problems if you don't care about
+ # hardware coherency (i.e., no virtualization or cache coherent DMA)
+ gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043
+
+[PcdsFeatureFlag.AARCH64, PcdsFeatureFlag.ARM]
+ ## Used to select method for requesting services from S-EL1.
+ # TRUE - Selects FF-A calls for communication between S-EL0 and SPMC.
+ # FALSE - Selects SVC calls for communication between S-EL0 and SPMC.
+ # @Prompt Enable FF-A support.
+ gArmTokenSpaceGuid.PcdFfaEnable|FALSE|BOOLEAN|0x0000005B
+
[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006
@@ -79,12 +154,7 @@
# Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor.
gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
- # This PCD will free the unallocated buffers if their size reach this threshold.
- # We set the default value to 512MB.
- gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000043
- gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
- gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
+ gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT64|0x00000004
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
#
@@ -109,18 +179,23 @@
gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
#
- # ARM L2x0 PCDs
+ # SMBIOS PCDs
#
- gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
+ gArmTokenSpaceGuid.PcdSystemProductName|L""|VOID*|0x30000053
+ gArmTokenSpaceGuid.PcdSystemVersion|L""|VOID*|0x30000054
+ gArmTokenSpaceGuid.PcdBaseBoardManufacturer|L""|VOID*|0x30000055
+ gArmTokenSpaceGuid.PcdBaseBoardProductName|L""|VOID*|0x30000056
+ gArmTokenSpaceGuid.PcdBaseBoardVersion|L""|VOID*|0x30000057
+ gArmTokenSpaceGuid.PcdProcessorManufacturer|L""|VOID*|0x30000071
+ gArmTokenSpaceGuid.PcdProcessorVersion|L""|VOID*|0x30000072
+ gArmTokenSpaceGuid.PcdProcessorSerialNumber|L""|VOID*|0x30000073
+ gArmTokenSpaceGuid.PcdProcessorAssetTag|L""|VOID*|0x30000074
+ gArmTokenSpaceGuid.PcdProcessorPartNumber|L""|VOID*|0x30000075
#
- # BdsLib
+ # ARM L2x0 PCDs
#
- gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E
- # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory
- gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F
- # Maximum file size for TFTP servers that do not support 'tsize' extension
- gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B
#
# ARM Normal (or Non Secure) Firmware PCDs
@@ -128,6 +203,14 @@
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E
+ #
+ # Value to add to a host address to obtain a device address, using
+ # unsigned 64-bit integer arithmetic on both ARM and AArch64. This
+ # means we can rely on truncation on overflow to specify negative
+ # offsets.
+ #
+ gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044
+
[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]
gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B
gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D
@@ -154,16 +237,6 @@
# By default we do not do a transition to non-secure mode
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
- # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory
- gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020
-
- # If the fixed FDT address is not available, then it should be loaded below the kernel.
- # The recommendation from the Linux kernel is to have the FDT below 16KB.
- # (see the kernel doc: Documentation/arm/Booting)
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
- # The FDT blob must be loaded at a 64bit aligned address.
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
-
# Non Secure Access Control Register
# - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
# - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
@@ -202,12 +275,6 @@
# Other modes include using SP0 or switching to Aarch32, but these are
# not currently supported.
gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
- # If the fixed FDT address is not available, then it should be loaded above the kernel.
- # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
- # (see the kernel doc: Documentation/arm64/booting.txt)
- gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
- # The FDT blob must be loaded at a 2MB aligned address.
- gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026
#
@@ -217,11 +284,17 @@
[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]
# System Memory (DRAM): These PCDs define the region of in-built system memory
- # Some platforms can get DRAM extensions, these additional regions will be declared
- # to UEFI by ArmPlatformLib
+ # Some platforms can get DRAM extensions, these additional regions may be
+ # declared to UEFI using separate resource descriptor HOBs
gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
+ gArmTokenSpaceGuid.PcdMmBufferBase|0|UINT64|0x00000045
+ gArmTokenSpaceGuid.PcdMmBufferSize|0|UINT64|0x00000046
+
+ gArmTokenSpaceGuid.PcdSystemBiosRelease|0xFFFF|UINT16|0x30000058
+ gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease|0xFFFF|UINT16|0x30000059
+
[PcdsFixedAtBuild.common, PcdsDynamic.common]
#
# ARM Architectural Timer
@@ -238,15 +311,81 @@
# ARM Generic Watchdog
#
- gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007
- gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008
gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009
#
# ARM Generic Interrupt Controller
#
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C
# Base address for the GIC Redistributor region that contains the boot CPU
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D
gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025
+
+ #
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
+ # Note that "IO" is just another MMIO range that simulates IO space; there
+ # are no special instructions to access it.
+ #
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
+ # specific to their containing address spaces. In order to get the physical
+ # address for the CPU, for a given access, the respective translation value
+ # has to be added.
+ #
+ # The translations always have to be initialized like this, using UINT64:
+ #
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
+ #
+ # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
+ #
+ # because (a) the target address space (ie. the cpu-physical space) is
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*
+ # arithmetic.
+ #
+ # Accordingly, the translation itself needs to be implemented as:
+ #
+ # UINT64 UntranslatedIoAddress; // input parameter
+ # UINT32 UntranslatedMmio32Address; // input parameter
+ # UINT64 UntranslatedMmio64Address; // input parameter
+ #
+ # UINT64 TranslatedIoAddress; // output parameter
+ # UINT64 TranslatedMmio32Address; // output parameter
+ # UINT64 TranslatedMmio64Address; // output parameter
+ #
+ # TranslatedIoAddress = UntranslatedIoAddress +
+ # gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation;
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation;
+ # TranslatedMmio64Address = UntranslatedMmio64Address +
+ # gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation;
+ #
+ # The modular arithmetic performed in UINT64 ensures that the translation
+ # works correctly regardless of the relation between IoCpuBase and
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
+ # PcdPciMmio64Base.
+ #
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050
+ gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057
+
+ #
+ # Inclusive range of allowed PCI buses.
+ #
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059
+ gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A
+
+[PcdsDynamicEx]
+ #
+ # This dynamic PCD hold the GUID of a firmware FFS which contains
+ # the LinuxBoot payload.
+ #
+ gArmTokenSpaceGuid.PcdLinuxBootFileGuid|{0x0}|VOID*|0x0000005C