X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FArmPkg.dec;h=e664f8626a4ca96461b6801f15176821cefe5204;hb=0086fca024d3ada1073a061f141ca898d8009ca9;hp=63445756d916d19ded4417c890ea8e8cde2f3286;hpb=1bfda055dfbc52678655ab2ded721f9f7c0cd496;p=mirror_edk2.git diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index 63445756d9..e664f8626a 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -2,6 +2,7 @@ # ARM processor package. # # Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
+# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -35,18 +36,23 @@ ArmLib|Include/Library/ArmLib.h SemihostLib|Include/Library/Semihosting.h UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h - DefaultExceptioHandlerLib|Include/Library/DefaultExceptioHandlerLib.h + DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h [Guids.common] gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } } + ## ARM MPCore table + # Include/Guid/ArmMpCoreInfo.h + gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } + +[Ppis] + ## Include/Ppi/ArmMpCoreInfo.h + gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} } + [Protocols.common] gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } } - ## Include/Protocol/MmcHost.h - gEfiMmcHostProtocolGuid = { 0x3e591c00, 0x9e4a, 0x11df, {0x92, 0x44, 0x00, 0x02, 0xA5, 0xD5, 0xC5, 0x1B }} - [PcdsFeatureFlag.common] gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001 @@ -55,65 +61,127 @@ # point the Exception Vector Table to its location in CpuDxe. # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress) gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022 + # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before + # it has been configured by the CPU DXE + gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032 + + # Define if the Power State Coordination Interface (PSCI) is supported by the Platform Trusted Firmware + gArmTokenSpaceGuid.PcdArmPsciSupport|FALSE|BOOLEAN|0x00000033 - gArmTokenSpaceGuid.PcdEfiUncachedMemoryToStronglyOrdered|FALSE|BOOLEAN|0x00000025 - gArmTokenSpaceGuid.PcdSkipPeiCore|FALSE|BOOLEAN|0x00000026 - [PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 + # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file. # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024 gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002 gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003 - gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xfff00000|UINT32|0x00000004 + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 - # - # ARM PL180 MCI - # - gArmTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000006 - gArmTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000007 - # # ARM PL390 General Interrupt Controller # gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D - gArmTokenSpaceGuid.PcdGicNumInterrupts|96|UINT32|0x00000023 + gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 # - # ARM Secure SEC PCDs + # ARM Secure Firmware PCDs # gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT32|0x00000015 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 + gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT32|0x0000002F + gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 # - # ARM MPCore MailBox PCDs + # ARM Normal (or Non Secure) Firmware PCDs # - # Address to Set/Get to Mailbox in Multicore system - gArmTokenSpaceGuid.PcdMPCoreMailboxSetAddress|0|UINT32|0x00000017 - gArmTokenSpaceGuid.PcdMPCoreMailboxGetAddress|0|UINT32|0x00000018 - # Address/Value to clear Mailbox in Multicore system - gArmTokenSpaceGuid.PcdMPCoreMailboxClearAddress|0|UINT32|0x00000019 - gArmTokenSpaceGuid.PcdMPCoreMailboxClearValue|0|UINT32|0x0000001A - + gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT32|0x0000002B + gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C + gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT32|0x0000002D + gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E + # - # ARM L2x0 PCDs + # ARM Hypervisor Firmware PCDs + # + gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A + gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B + gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C + gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D + + # + # ARM Security Extension # - gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B + # Secure Configuration Register + # - BIT0 : NS - Non Secure bit + # - BIT1 : IRQ Handler + # - BIT2 : FIQ Handler + # - BIT3 : EA - External Abort + # - BIT4 : FW - F bit writable + # - BIT5 : AW - A bit writable + # - BIT6 : nET - Not Early Termination + # - BIT7 : SCD - Secure Monitor Call Disable + # - BIT8 : HCE - Hyp Call enable + # - BIT9 : SIF - Secure Instruction Fetch + # 0x31 = NS | EA | FW + gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038 + + # Non Secure Access Control Register + # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality + # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 + # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable + # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable + # 0xC00 = cp10 | cp11 + gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039 + + # System Memory (DRAM): These PCDs define the region of in-built system memory + # Some platforms can get DRAM extensions, these additional regions will be declared + # to UEFI by ArmPLatformPlib + gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029 + gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A + + # Use ClusterId + CoreId to identify the PrimaryCore + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031 + # The Primary Core is ClusterId[0] & CoreId[0] + gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037 + # Number of the CPU Interface for the Primary Core (eg: The number for the CPU0 of + # Cluster1 might be 4 if the implementer had followed the convention: Cpu Interface + # = 4 * Cluster) + gArmTokenSpaceGuid.PcdGicPrimaryCoreId|0|UINT32|0x00000043 + # - # ARM PL390 General Interrupt Controller + # ARM L2x0 PCDs # - gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000001C - gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000001D + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B # # BdsLib # gArmTokenSpaceGuid.PcdArmMachineType|0|UINT32|0x0000001E - gArmTokenSpaceGuid.PcdLinuxKernelDP|L""|VOID*|0x0000001F - gArmTokenSpaceGuid.PcdLinuxAtag|""|VOID*|0x00000020 - gArmTokenSpaceGuid.PcdFdtDP|L""|VOID*|0x00000021 + # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory + gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F + + # + # ARM Architectural Timer + # + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034 + # ARM Architectural Timer Interrupt(GIC PPI) number + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036 + +[PcdsFixedAtBuild.ARM] + # By default we do not do a transition to non-secure mode + gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E + + # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory + gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020 + # If the fixed FDT address is not available, then it should be loaded below the kernel. + # The recommendation from the Linux kernel is to have the FDT below 16KB. + # (see the kernel doc: Documentation/arm/Booting) + gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023 + # The FDT blob must be loaded at a 64bit aligned address. + gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026