X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FArmPkg.dec;h=f11243f236058b81b42b245a47f260ac279a80ff;hb=f20fc992aee02c54404b68c46abd30ffbdd9888e;hp=e664f8626a4ca96461b6801f15176821cefe5204;hpb=2425e1d4fea9f25cfee2497595149b451d91296d;p=mirror_edk2.git

diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec
index e664f8626a..f11243f236 100644
--- a/ArmPkg/ArmPkg.dec
+++ b/ArmPkg/ArmPkg.dec
@@ -81,7 +81,7 @@
   gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
   
   #
-  # ARM PL390 General Interrupt Controller
+  # ARM General Interrupt Controller
   #
   gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C
   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D
@@ -110,47 +110,17 @@
   gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B
   gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C
   gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D
- 
-  #
-  # ARM Security Extension
-  #
-  
-  # Secure Configuration Register
-  # - BIT0 : NS - Non Secure bit 
-  # - BIT1 : IRQ Handler
-  # - BIT2 : FIQ Handler
-  # - BIT3 : EA - External Abort
-  # - BIT4 : FW - F bit writable
-  # - BIT5 : AW - A bit writable
-  # - BIT6 : nET - Not Early Termination
-  # - BIT7 : SCD - Secure Monitor Call Disable
-  # - BIT8 : HCE - Hyp Call enable
-  # - BIT9 : SIF - Secure Instruction Fetch
-  # 0x31 = NS | EA | FW
-  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
-  
-  # Non Secure Access Control Register
-  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
-  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 
-  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
-  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
-  # 0xC00 = cp10 | cp11
-  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
-  
+
   # System Memory (DRAM): These PCDs define the region of in-built system memory
   # Some platforms can get DRAM extensions, these additional regions will be declared
   # to UEFI by ArmPLatformPlib   
-  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029
-  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A
 
   # Use ClusterId + CoreId to identify the PrimaryCore
   gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031
   # The Primary Core is ClusterId[0] & CoreId[0] 
   gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037
-  # Number of the CPU Interface for the Primary Core (eg: The number for the CPU0 of
-  # Cluster1 might be 4 if the implementer had followed the convention: Cpu Interface
-  # = 4 * Cluster)
-  gArmTokenSpaceGuid.PcdGicPrimaryCoreId|0|UINT32|0x00000043
 
   #
   # ARM L2x0 PCDs
@@ -173,6 +143,24 @@
   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036
 
 [PcdsFixedAtBuild.ARM]
+  #
+  # ARM Security Extension
+  #
+
+  # Secure Configuration Register
+  # - BIT0 : NS - Non Secure bit
+  # - BIT1 : IRQ Handler
+  # - BIT2 : FIQ Handler
+  # - BIT3 : EA - External Abort
+  # - BIT4 : FW - F bit writable
+  # - BIT5 : AW - A bit writable
+  # - BIT6 : nET - Not Early Termination
+  # - BIT7 : SCD - Secure Monitor Call Disable
+  # - BIT8 : HCE - Hyp Call enable
+  # - BIT9 : SIF - Secure Instruction Fetch
+  # 0x31 = NS | EA | FW
+  gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038
+
   # By default we do not do a transition to non-secure mode
   gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E
 
@@ -185,3 +173,48 @@
   gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023
   # The FDT blob must be loaded at a 64bit aligned address.
   gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026
+
+  # Non Secure Access Control Register
+  # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality
+  # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31
+  # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable
+  # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable
+  # 0xC00 = cp10 | cp11
+  gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039
+
+[PcdsFixedAtBuild.AARCH64]
+  #
+  # AArch64 Security Extension
+  #
+
+  # Secure Configuration Register
+  # - BIT0 : NS - Non Secure bit
+  # - BIT1 : IRQ Handler
+  # - BIT2 : FIQ Handler
+  # - BIT3 : EA - External Abort
+  # - BIT4 : FW - F bit writable
+  # - BIT5 : AW - A bit writable
+  # - BIT6 : nET - Not Early Termination
+  # - BIT7 : SCD - Secure Monitor Call Disable
+  # - BIT8 : HCE - Hyp Call enable
+  # - BIT9 : SIF - Secure Instruction Fetch
+  # - BIT10: RW -  Register width control for lower exception levels
+  # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer
+  # - BIT12: TWI - Trap WFI
+  # - BIT13: TWE - Trap WFE
+  # 0x501 = NS | HCE | RW
+  gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038
+
+  # By default we do transition to EL2 non-secure mode with Stack for EL2.
+  #        Mode Description              Bits
+  # NS EL2 SP2 all interupts disabled =  0x3c9
+  # NS EL1 SP1 all interupts disabled =  0x3c5
+  # Other modes include using SP0 or switching to Aarch32, but these are
+  # not currently supported.
+  gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E
+  # If the fixed FDT address is not available, then it should be loaded above the kernel.
+  # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.
+  # (see the kernel doc: Documentation/arm64/booting.txt)
+  gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023
+  # The FDT blob must be loaded at a 2MB aligned address.
+  gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026