X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FDrivers%2FArmGic%2FArmGicLib.c;h=58ab45f812b337dc1e607ed50c93f17c49b66305;hb=429309e0c6b74792d679681a8edd0d5ae0ff850c;hp=bd4b5edb903f3846f4f0e431f93e001f01cd9e7d;hpb=7c2a6033c149625482a18cd51b65513c8fb8fe15;p=mirror_edk2.git diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c index bd4b5edb90..58ab45f812 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -24,13 +24,13 @@ + ARM_GICR_SGI_VLPI_FRAME_SIZE \ + ARM_GICR_SGI_RESERVED_FRAME_SIZE) -#define ISENABLER_ADDRESS(base,offset) ((base) + \ +#define ISENABLER_ADDRESS(base, offset) ((base) +\ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset)) -#define ICENABLER_ADDRESS(base,offset) ((base) + \ +#define ICENABLER_ADDRESS(base, offset) ((base) +\ ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset)) -#define IPRIORITY_ADDRESS(base,offset) ((base) + \ +#define IPRIORITY_ADDRESS(base, offset) ((base) +\ ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset)) /** @@ -57,15 +57,15 @@ SourceIsSpi ( STATIC UINTN GicGetCpuRedistributorBase ( - IN UINTN GicRedistributorBase, - IN ARM_GIC_ARCH_REVISION Revision + IN UINTN GicRedistributorBase, + IN ARM_GIC_ARCH_REVISION Revision ) { - UINTN MpId; - UINTN CpuAffinity; - UINTN Affinity; - UINTN GicCpuRedistributorBase; - UINT64 TypeRegister; + UINTN MpId; + UINTN CpuAffinity; + UINTN Affinity; + UINTN GicCpuRedistributorBase; + UINT64 TypeRegister; MpId = ArmReadMpidr (); // Define CPU affinity as: @@ -83,7 +83,7 @@ GicGetCpuRedistributorBase ( do { TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER); - Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister); + Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister); if (Affinity == CpuAffinity) { return GicCpuRedistributorBase; } @@ -107,7 +107,7 @@ GicGetCpuRedistributorBase ( UINTN EFIAPI ArmGicGetInterfaceIdentification ( - IN INTN GicInterruptInterfaceBase + IN INTN GicInterruptInterfaceBase ) { // Read the GIC Identification Register @@ -117,10 +117,10 @@ ArmGicGetInterfaceIdentification ( UINTN EFIAPI ArmGicGetMaxNumInterrupts ( - IN INTN GicDistributorBase + IN INTN GicDistributorBase ) { - UINTN ItLines; + UINTN ItLines; ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F; @@ -133,10 +133,10 @@ ArmGicGetMaxNumInterrupts ( VOID EFIAPI ArmGicSendSgiTo ( - IN INTN GicDistributorBase, - IN INTN TargetListFilter, - IN INTN CPUTargetList, - IN INTN SgiId + IN INTN GicDistributorBase, + IN INTN TargetListFilter, + IN INTN CPUTargetList, + IN INTN SgiId ) { MmioWrite32 ( @@ -162,12 +162,12 @@ ArmGicSendSgiTo ( UINTN EFIAPI ArmGicAcknowledgeInterrupt ( - IN UINTN GicInterruptInterfaceBase, - OUT UINTN *InterruptId + IN UINTN GicInterruptInterfaceBase, + OUT UINTN *InterruptId ) { - UINTN Value; - ARM_GIC_ARCH_REVISION Revision; + UINTN Value; + ARM_GIC_ARCH_REVISION Revision; Revision = ArmGicGetSupportedArchRevision (); if (Revision == ARM_GIC_ARCH_REVISION_2) { @@ -193,11 +193,11 @@ ArmGicAcknowledgeInterrupt ( VOID EFIAPI ArmGicEndOfInterrupt ( - IN UINTN GicInterruptInterfaceBase, - IN UINTN Source + IN UINTN GicInterruptInterfaceBase, + IN UINTN Source ) { - ARM_GIC_ARCH_REVISION Revision; + ARM_GIC_ARCH_REVISION Revision; Revision = ArmGicGetSupportedArchRevision (); if (Revision == ARM_GIC_ARCH_REVISION_2) { @@ -212,25 +212,26 @@ ArmGicEndOfInterrupt ( VOID EFIAPI ArmGicSetInterruptPriority ( - IN UINTN GicDistributorBase, - IN UINTN GicRedistributorBase, - IN UINTN Source, - IN UINTN Priority + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source, + IN UINTN Priority ) { - UINT32 RegOffset; - UINTN RegShift; - ARM_GIC_ARCH_REVISION Revision; - UINTN GicCpuRedistributorBase; + UINT32 RegOffset; + UINTN RegShift; + ARM_GIC_ARCH_REVISION Revision; + UINTN GicCpuRedistributorBase; // Calculate register offset and bit position RegOffset = Source / 4; - RegShift = (Source % 4) * 8; + RegShift = (Source % 4) * 8; Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) || - SourceIsSpi (Source)) { + SourceIsSpi (Source)) + { MmioAndThenOr32 ( GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset), ~(0xff << RegShift), @@ -256,24 +257,25 @@ ArmGicSetInterruptPriority ( VOID EFIAPI ArmGicEnableInterrupt ( - IN UINTN GicDistributorBase, - IN UINTN GicRedistributorBase, - IN UINTN Source + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source ) { - UINT32 RegOffset; - UINTN RegShift; - ARM_GIC_ARCH_REVISION Revision; - UINTN GicCpuRedistributorBase; + UINT32 RegOffset; + UINTN RegShift; + ARM_GIC_ARCH_REVISION Revision; + UINTN GicCpuRedistributorBase; // Calculate enable register offset and bit position RegOffset = Source / 32; - RegShift = Source % 32; + RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) || - SourceIsSpi (Source)) { + SourceIsSpi (Source)) + { // Write set-enable register MmioWrite32 ( GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), @@ -291,7 +293,7 @@ ArmGicEnableInterrupt ( // Write set-enable register MmioWrite32 ( - ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset), + ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset), 1 << RegShift ); } @@ -300,24 +302,25 @@ ArmGicEnableInterrupt ( VOID EFIAPI ArmGicDisableInterrupt ( - IN UINTN GicDistributorBase, - IN UINTN GicRedistributorBase, - IN UINTN Source + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source ) { - UINT32 RegOffset; - UINTN RegShift; - ARM_GIC_ARCH_REVISION Revision; - UINTN GicCpuRedistributorBase; + UINT32 RegOffset; + UINTN RegShift; + ARM_GIC_ARCH_REVISION Revision; + UINTN GicCpuRedistributorBase; // Calculate enable register offset and bit position RegOffset = Source / 32; - RegShift = Source % 32; + RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) || - SourceIsSpi (Source)) { + SourceIsSpi (Source)) + { // Write clear-enable register MmioWrite32 ( GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), @@ -325,16 +328,16 @@ ArmGicDisableInterrupt ( ); } else { GicCpuRedistributorBase = GicGetCpuRedistributorBase ( - GicRedistributorBase, - Revision - ); + GicRedistributorBase, + Revision + ); if (GicCpuRedistributorBase == 0) { return; } // Write clear-enable register MmioWrite32 ( - ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset), + ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset), 1 << RegShift ); } @@ -343,29 +346,30 @@ ArmGicDisableInterrupt ( BOOLEAN EFIAPI ArmGicIsInterruptEnabled ( - IN UINTN GicDistributorBase, - IN UINTN GicRedistributorBase, - IN UINTN Source + IN UINTN GicDistributorBase, + IN UINTN GicRedistributorBase, + IN UINTN Source ) { - UINT32 RegOffset; - UINTN RegShift; - ARM_GIC_ARCH_REVISION Revision; - UINTN GicCpuRedistributorBase; - UINT32 Interrupts; + UINT32 RegOffset; + UINTN RegShift; + ARM_GIC_ARCH_REVISION Revision; + UINTN GicCpuRedistributorBase; + UINT32 Interrupts; // Calculate enable register offset and bit position RegOffset = Source / 32; - RegShift = Source % 32; + RegShift = Source % 32; Revision = ArmGicGetSupportedArchRevision (); if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy) || - SourceIsSpi (Source)) { + SourceIsSpi (Source)) + { Interrupts = ((MmioRead32 ( GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset) ) - & (1 << RegShift)) != 0); + & (1 << RegShift)) != 0); } else { GicCpuRedistributorBase = GicGetCpuRedistributorBase ( GicRedistributorBase, @@ -377,7 +381,7 @@ ArmGicIsInterruptEnabled ( // Read set-enable register Interrupts = MmioRead32 ( - ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset) + ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset) ); } @@ -387,7 +391,7 @@ ArmGicIsInterruptEnabled ( VOID EFIAPI ArmGicDisableDistributor ( - IN INTN GicDistributorBase + IN INTN GicDistributorBase ) { // Disable Gic Distributor @@ -397,10 +401,10 @@ ArmGicDisableDistributor ( VOID EFIAPI ArmGicEnableInterruptInterface ( - IN INTN GicInterruptInterfaceBase + IN INTN GicInterruptInterfaceBase ) { - ARM_GIC_ARCH_REVISION Revision; + ARM_GIC_ARCH_REVISION Revision; Revision = ArmGicGetSupportedArchRevision (); if (Revision == ARM_GIC_ARCH_REVISION_2) { @@ -415,10 +419,10 @@ ArmGicEnableInterruptInterface ( VOID EFIAPI ArmGicDisableInterruptInterface ( - IN INTN GicInterruptInterfaceBase + IN INTN GicInterruptInterfaceBase ) { - ARM_GIC_ARCH_REVISION Revision; + ARM_GIC_ARCH_REVISION Revision; Revision = ArmGicGetSupportedArchRevision (); if (Revision == ARM_GIC_ARCH_REVISION_2) {