X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FDrivers%2FPL390Gic%2FPL390GicNonSec.c;h=c2089fe8466c034c80ab63a01632b56c9cec0038;hb=438311a3bd32df6ab0352da55d3391fc8da3ae4e;hp=526af02d3ee23caa829f99545eff9beeea7dbf05;hpb=2ac288f9199196dfc4ab05bee0a7815ca361174a;p=mirror_edk2.git

diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
index 526af02d3e..c2089fe846 100644
--- a/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
+++ b/ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
@@ -12,6 +12,7 @@
 *
 **/
 
+#include <Uefi.h>
 #include <Library/IoLib.h>
 #include <Drivers/PL390Gic.h>
 
@@ -23,10 +24,10 @@ PL390GicEnableInterruptInterface (
   )
 {  
   /*
-   * Enable the CPU interface in Non-Secure world
-   * Note: The ICCICR register is banked when Security extensions are implemented   
-   */
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
+  * Enable the CPU interface in Non-Secure world
+  * Note: The ICCICR register is banked when Security extensions are implemented
+  */
+  MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);
 }
 
 VOID
@@ -35,11 +36,11 @@ PL390GicEnableDistributor (
   IN  INTN          GicDistributorBase
   )
 {
-    /*
-     * Enable GIC distributor in Non-Secure world.
-     * Note: The ICDDCR register is banked when Security extensions are implemented
-     */
-    MmioWrite32(GicDistributorBase + GIC_ICDDCR, 0x00000001);
+  /*
+   * Enable GIC distributor in Non-Secure world.
+   * Note: The ICDDCR register is banked when Security extensions are implemented
+   */
+  MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);
 }
 
 VOID
@@ -50,7 +51,7 @@ PL390GicSendSgiTo (
   IN  INTN          CPUTargetList
   )
 {
-  MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
+  MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));
 }
 
 UINT32
@@ -60,18 +61,18 @@ PL390GicAcknowledgeSgiFrom (
   IN  INTN          CoreId
   )
 {
-    INTN            InterruptId;
+  INTN            InterruptId;
 
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+  InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);
 
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
   if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
-        return 1;
-    } else {
-        return 0;
-    }
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+    MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+    return 1;
+  } else {
+    return 0;
+  }
 }
 
 UINT32
@@ -82,16 +83,16 @@ PL390GicAcknowledgeSgi2From (
   IN  INTN          SgiId
   )
 {
-    INTN            InterruptId;
+  INTN            InterruptId;
 
-    InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
+  InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);
 
-    //Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
+  // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID
   if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {
-      //Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
-    MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
-        return 1;
-    } else {
-        return 0;
-    }
+    // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR
+    MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);
+    return 1;
+  } else {
+    return 0;
+  }
 }