X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FInclude%2FChipset%2FArmV7.h;h=94620c087df2965f0028320e571b2ea002d49233;hb=429309e0c6b74792d679681a8edd0d5ae0ff850c;hp=6b20b988e364d4f01e5edb5b9d7a46ed7f35567a;hpb=7c2a6033c149625482a18cd51b65513c8fb8fe15;p=mirror_edk2.git

diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h
index 6b20b988e3..94620c087d 100644
--- a/ArmPkg/Include/Chipset/ArmV7.h
+++ b/ArmPkg/Include/Chipset/ArmV7.h
@@ -13,19 +13,19 @@
 #include <Chipset/ArmV7Mmu.h>
 
 // ARM Interrupt ID in Exception Table
-#define ARM_ARCH_EXCEPTION_IRQ            EXCEPT_ARM_IRQ
+#define ARM_ARCH_EXCEPTION_IRQ  EXCEPT_ARM_IRQ
 
 // ID_PFR1 - ARM Processor Feature Register 1 definitions
-#define ARM_PFR1_SEC        (0xFUL << 4)
-#define ARM_PFR1_TIMER      (0xFUL << 16)
-#define ARM_PFR1_GIC        (0xFUL << 28)
+#define ARM_PFR1_SEC    (0xFUL << 4)
+#define ARM_PFR1_TIMER  (0xFUL << 16)
+#define ARM_PFR1_GIC    (0xFUL << 28)
 
 // Domain Access Control Register
-#define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MASK(a)      (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_NONE(a)      (0UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a)    (1UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a)  (2UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a)   (3UL << (2 * (a)))
 
 // CPSR - Coprocessor Status Register definitions
 #define CPSR_MODE_USER       0x10
@@ -41,48 +41,47 @@
 #define CPSR_IRQ             (1 << 7)
 #define CPSR_FIQ             (1 << 6)
 
-
 // CPACR - Coprocessor Access Control Register definitions
-#define CPACR_CP_DENIED(cp)     0x00
-#define CPACR_CP_PRIV(cp)       ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
-#define CPACR_CP_FULL(cp)       ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
-#define CPACR_ASEDIS            (1 << 31)
-#define CPACR_D32DIS            (1 << 30)
-#define CPACR_CP_FULL_ACCESS    0x0FFFFFFF
+#define CPACR_CP_DENIED(cp)  0x00
+#define CPACR_CP_PRIV(cp)    ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_CP_FULL(cp)    ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_ASEDIS          (1 << 31)
+#define CPACR_D32DIS          (1 << 30)
+#define CPACR_CP_FULL_ACCESS  0x0FFFFFFF
 
 // NSACR - Non-Secure Access Control Register definitions
-#define NSACR_CP(cp)            ((1 << (cp)) & 0x3FFF)
-#define NSACR_NSD32DIS          (1 << 14)
-#define NSACR_NSASEDIS          (1 << 15)
-#define NSACR_PLE               (1 << 16)
-#define NSACR_TL                (1 << 17)
-#define NSACR_NS_SMP            (1 << 18)
-#define NSACR_RFR               (1 << 19)
+#define NSACR_CP(cp)  ((1 << (cp)) & 0x3FFF)
+#define NSACR_NSD32DIS  (1 << 14)
+#define NSACR_NSASEDIS  (1 << 15)
+#define NSACR_PLE       (1 << 16)
+#define NSACR_TL        (1 << 17)
+#define NSACR_NS_SMP    (1 << 18)
+#define NSACR_RFR       (1 << 19)
 
 // SCR - Secure Configuration Register definitions
-#define SCR_NS                  (1 << 0)
-#define SCR_IRQ                 (1 << 1)
-#define SCR_FIQ                 (1 << 2)
-#define SCR_EA                  (1 << 3)
-#define SCR_FW                  (1 << 4)
-#define SCR_AW                  (1 << 5)
+#define SCR_NS   (1 << 0)
+#define SCR_IRQ  (1 << 1)
+#define SCR_FIQ  (1 << 2)
+#define SCR_EA   (1 << 3)
+#define SCR_FW   (1 << 4)
+#define SCR_AW   (1 << 5)
 
 // MIDR - Main ID Register definitions
-#define ARM_CPU_TYPE_SHIFT      4
-#define ARM_CPU_TYPE_MASK       0xFFF
-#define ARM_CPU_TYPE_AEMV8      0xD0F
-#define ARM_CPU_TYPE_A53        0xD03
-#define ARM_CPU_TYPE_A57        0xD07
-#define ARM_CPU_TYPE_A15        0xC0F
-#define ARM_CPU_TYPE_A12        0xC0D
-#define ARM_CPU_TYPE_A9         0xC09
-#define ARM_CPU_TYPE_A7         0xC07
-#define ARM_CPU_TYPE_A5         0xC05
-
-#define ARM_CPU_REV_MASK        ((0xF << 20) | (0xF) )
-#define ARM_CPU_REV(rn, pn)     ((((rn) & 0xF) << 20) | ((pn) & 0xF))
-
-#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
+#define ARM_CPU_TYPE_SHIFT  4
+#define ARM_CPU_TYPE_MASK   0xFFF
+#define ARM_CPU_TYPE_AEMV8  0xD0F
+#define ARM_CPU_TYPE_A53    0xD03
+#define ARM_CPU_TYPE_A57    0xD07
+#define ARM_CPU_TYPE_A15    0xC0F
+#define ARM_CPU_TYPE_A12    0xC0D
+#define ARM_CPU_TYPE_A9     0xC09
+#define ARM_CPU_TYPE_A7     0xC07
+#define ARM_CPU_TYPE_A5     0xC05
+
+#define ARM_CPU_REV_MASK  ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn)  ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+
+#define ARM_VECTOR_TABLE_ALIGNMENT  ((1 << 5)-1)
 
 VOID
 EFIAPI
@@ -105,7 +104,7 @@ ArmReadTpidrurw (
 VOID
 EFIAPI
 ArmWriteTpidrurw (
-  UINTN Value
+  UINTN  Value
   );
 
 UINT32
@@ -117,7 +116,7 @@ ArmReadNsacr (
 VOID
 EFIAPI
 ArmWriteNsacr (
-  IN  UINT32   Nsacr
+  IN  UINT32  Nsacr
   );
 
 #endif // ARM_V7_H_