X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FInclude%2FLibrary%2FArmGicLib.h;h=e2a4818c4c0c62fd74aff9bba8df91222a21cde4;hb=f6d46e296060507bc8d02fadb8ebd591fc9aefca;hp=3280cf8eeb2f03e95996ffea2895b0b3f09965d2;hpb=017baa1cf380ce9fd00e39bc89e6067d8bf5112b;p=mirror_edk2.git

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 3280cf8eeb..e2a4818c4c 100644
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -1,6 +1,6 @@
 /** @file
 *
-*  Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
 *
 *  This program and the accompanying materials
 *  are licensed and made available under the terms and conditions of the BSD License
@@ -18,6 +18,10 @@
 //
 // GIC definitions
 //
+typedef enum {
+  ARM_GIC_ARCH_REVISION_2,
+  ARM_GIC_ARCH_REVISION_3
+} ARM_GIC_ARCH_REVISION;
 
 //
 // GIC Distributor
@@ -26,7 +30,7 @@
 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register
 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register
 
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)
+// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
 #define ARM_GIC_ICDISR          0x080 // Interrupt Security Registers
 #define ARM_GIC_ICDISER         0x100 // Interrupt Set-Enable Registers
 #define ARM_GIC_ICDICER         0x180 // Interrupt Clear-Enable Registers
@@ -34,10 +38,10 @@
 #define ARM_GIC_ICDICPR         0x280 // Interrupt Clear-Pending Registers
 #define ARM_GIC_ICDABR          0x300 // Active Bit Registers
 
-// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES
+// Each reg base below repeats for Number of interrupts / 4
 #define ARM_GIC_ICDIPR          0x400 // Interrupt Priority Registers
 
-// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS
+// Each reg base below repeats for Number of interrupts
 #define ARM_GIC_ICDIPTR         0x800 // Interrupt Processor Target Registers
 #define ARM_GIC_ICDICFR         0xC00 // Interrupt Configuration Registers
 
@@ -46,6 +50,26 @@
 // just one of these
 #define ARM_GIC_ICDSGIR         0xF00 // Software Generated Interrupt Register
 
+// GICv3 specific registers
+#define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers
+
+// the Affinity Routing Enable (ARE) bit in GICD_CTLR
+#define ARM_GIC_ICDDCR_ARE      (1 << 4)
+
+//
+// GIC Redistributor
+//
+
+#define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
+
+// GIC Redistributor Control frame
+#define ARM_GICR_TYPER          0x0008  // Redistributor Type Register
+
+// GIC SGI & PPI Redistributor frame
+#define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers
+#define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers
+
 //
 // GIC Cpu interface
 //
@@ -57,7 +81,7 @@
 #define ARM_GIC_ICCRPR          0x14  // Running Priority Register
 #define ARM_GIC_ICCPIR          0x18  // Highest Pending Interrupt Register
 #define ARM_GIC_ICCABPR         0x1C  // Aliased Binary Point Register
-#define ARM_GIC_ICCIDR          0xFC  // Identification Register
+#define ARM_GIC_ICCIIDR         0xFC  // Identification Register
 
 #define ARM_GIC_ICDSGIR_FILTER_TARGETLIST       0x0
 #define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE     0x1
@@ -71,10 +95,25 @@
 #define ARM_GIC_ICCICR_USE_SBPR                 0x10
 
 // Bit Mask for GICC_IIDR
-#define ARM_GIC_ICCIDR_GET_PRODUCT_ID(IccIdr)   (((IccIdr) >> 20) & 0xFFF)
-#define ARM_GIC_ICCIDR_GET_ARCH_VERSION(IccIdr) (((IccIdr) >> 16) & 0xF)
-#define ARM_GIC_ICCIDR_GET_REVISION(IccIdr)     (((IccIdr) >> 12) & 0xF)
-#define ARM_GIC_ICCIDR_GET_IMPLEMENTER(IccIdr)  ((IccIdr) & 0xFFF)
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr)   (((IccIidr) >> 20) & 0xFFF)
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr)     (((IccIidr) >> 12) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr)  ((IccIidr) & 0xFFF)
+
+// Bit Mask for
+#define ARM_GIC_ICCIAR_ACKINTID                 0x3FF
+
+ARM_GIC_ARCH_REVISION
+EFIAPI
+ArmGicGetSupportedArchRevision (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmGicGetInterfaceIdentification (
+  IN  INTN          GicInterruptInterfaceBase
+  );
 
 //
 // GIC Secure interfaces
@@ -113,6 +152,12 @@ ArmGicEnableDistributor (
   IN  INTN          GicDistributorBase
   );
 
+VOID
+EFIAPI
+ArmGicDisableDistributor (
+  IN  INTN          GicDistributorBase
+  );
+
 UINTN
 EFIAPI
 ArmGicGetMaxNumInterrupts (
@@ -128,15 +173,33 @@ ArmGicSendSgiTo (
   IN  INTN          SgiId
   );
 
-RETURN_STATUS
+/*
+ * Acknowledge and return the value of the Interrupt Acknowledge Register
+ *
+ * InterruptId is returned separately from the register value because in
+ * the GICv2 the register value contains the CpuId and InterruptId while
+ * in the GICv3 the register value is only the InterruptId.
+ *
+ * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface
+ * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register
+ *
+ * @retval value returned by the Interrupt Acknowledge Register
+ *
+ */
+UINTN
 EFIAPI
 ArmGicAcknowledgeInterrupt (
-  IN  UINTN          GicDistributorBase,
   IN  UINTN          GicInterruptInterfaceBase,
-  OUT UINTN          *CoreId,
   OUT UINTN          *InterruptId
   );
 
+VOID
+EFIAPI
+ArmGicEndOfInterrupt (
+  IN  UINTN                 GicInterruptInterfaceBase,
+  IN UINTN                  Source
+  );
+
 UINTN
 EFIAPI
 ArmGicSetPriorityMask (
@@ -144,4 +207,28 @@ ArmGicSetPriorityMask (
   IN  INTN          PriorityMask
   );
 
+VOID
+EFIAPI
+ArmGicEnableInterrupt (
+  IN UINTN                  GicDistributorBase,
+  IN UINTN                  GicRedistributorBase,
+  IN UINTN                  Source
+  );
+
+VOID
+EFIAPI
+ArmGicDisableInterrupt (
+  IN UINTN                  GicDistributorBase,
+  IN UINTN                  GicRedistributorBase,
+  IN UINTN                  Source
+  );
+
+BOOLEAN
+EFIAPI
+ArmGicIsInterruptEnabled (
+  IN UINTN                  GicDistributorBase,
+  IN UINTN                  GicRedistributorBase,
+  IN UINTN                  Source
+  );
+
 #endif