X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FInclude%2FLibrary%2FArmLib.h;h=0bb0d4a0639a27ad716a4e1cbc55d6086d81ba14;hb=3402aac7d985bf8a9f9d3c639f3fe93609380513;hp=9694b9d06d0f9408cebe5db66abc8da72fbe721b;hpb=0ff0e414d13afd3cad5017a98bc1e257f64ed6d4;p=mirror_edk2.git

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 9694b9d06d..0bb0d4a063 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -123,9 +123,6 @@ typedef enum {
 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
-// Get the position of the core for the Stack Offset (4 Core per Cluster)
-//   Position = (ClusterId * 4) + CoreId
-#define GET_CORE_POS(MpId)    ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 
 ARM_CACHE_TYPE
@@ -151,43 +148,43 @@ EFIAPI
 ArmDataCachePresent (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheSize (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheAssociativity (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmDataCacheLineLength (
   VOID
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmInstructionCachePresent (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheSize (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheAssociativity (
   VOID
   );
-  
+
 UINTN
 EFIAPI
 ArmInstructionCacheLineLength (
@@ -212,15 +209,9 @@ ArmReadIdPfr1 (
   VOID
   );
 
-UINT32
-EFIAPI
-Cp15IdCode (
-  VOID
-  );
-  
-UINT32
+UINTN
 EFIAPI
-Cp15CacheInfo (
+ArmCacheInfo (
   VOID
   );
 
@@ -320,7 +311,7 @@ EFIAPI
 ArmDisableInstructionCache (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmEnableMmu (
@@ -404,7 +395,7 @@ EFIAPI
 ArmDisableFiq (
   VOID
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmGetFiqState (
@@ -416,14 +407,14 @@ EFIAPI
 ArmInvalidateTlb (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmUpdateTranslationTableEntry (
   IN  VOID     *TranslationTableEntry,
   IN  VOID     *Mva
   );
-  
+
 VOID
 EFIAPI
 ArmSetDomainAccessControl (
@@ -449,25 +440,13 @@ ArmConfigureMmu (
   OUT VOID                         **TranslationTableBase OPTIONAL,
   OUT UINTN                         *TranslationTableSize  OPTIONAL
   );
-  
+
 BOOLEAN
 EFIAPI
 ArmMmuEnabled (
   VOID
   );
-  
-VOID
-EFIAPI
-ArmSwitchProcessorMode (
-  IN ARM_PROCESSOR_MODE Mode
-  );
 
-ARM_PROCESSOR_MODE
-EFIAPI
-ArmProcessorMode (
-  VOID
-  );
-  
 VOID
 EFIAPI
 ArmEnableBranchPrediction (
@@ -503,13 +482,13 @@ EFIAPI
 ArmDataMemoryBarrier (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmDataSyncronizationBarrier (
   VOID
   );
-  
+
 VOID
 EFIAPI
 ArmInstructionSynchronizationBarrier (
@@ -601,16 +580,28 @@ ArmEnableVFP (
   VOID
   );
 
+/**
+  Get the Secure Configuration Register value
+
+  @return   Value read from the Secure Configuration Register
+
+**/
 UINT32
 EFIAPI
 ArmReadScr (
   VOID
   );
 
+/**
+  Set the Secure Configuration Register
+
+  @param Value   Value to write to the Secure Configuration Register
+
+**/
 VOID
 EFIAPI
 ArmWriteScr (
-  IN  UINT32   SetWayFormat
+  IN  UINT32   Value
   );
 
 UINT32
@@ -643,4 +634,33 @@ ArmWriteHVBar (
   IN  UINTN   HypModeVectorBase
   );
 
+
+//
+// Helper functions for accessing CPU ACTLR
+//
+
+UINTN
+EFIAPI
+ArmReadCpuActlr (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmWriteCpuActlr (
+  IN  UINTN Val
+  );
+
+VOID
+EFIAPI
+ArmSetCpuActlrBit (
+  IN  UINTN    Bits
+  );
+
+VOID
+EFIAPI
+ArmUnsetCpuActlrBit (
+  IN  UINTN    Bits
+  );
+
 #endif // __ARM_LIB__