X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FLibrary%2FArmLib%2FArmV7%2FArmV7Support.S;h=5f030d92de3111f274f36aab9aec0b36991dbd21;hb=3b1495156a3576992b31a77e799db207cb61d9de;hp=fb1ca2dee244e142b65184dc54d6c87ed2f3dec7;hpb=bd6b97994ab6219c74033a7e68a503dbb8d56f9f;p=mirror_edk2.git diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index fb1ca2dee2..5f030d92de 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -1,7 +1,7 @@ -#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
-# Copyright (c) 2011, ARM Limited. All rights reserved. +# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -23,7 +23,6 @@ GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmDrainWriteBuffer) GCC_ASM_EXPORT (ArmEnableMmu) GCC_ASM_EXPORT (ArmDisableMmu) GCC_ASM_EXPORT (ArmDisableCachesAndMmu) @@ -39,18 +38,19 @@ GCC_ASM_EXPORT (ArmSetLowVectors) GCC_ASM_EXPORT (ArmSetHighVectors) GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) GCC_ASM_EXPORT (ArmDataMemoryBarrier) -GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) +GCC_ASM_EXPORT (ArmDataSynchronizationBarrier) GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) +GCC_ASM_EXPORT (ArmReadVBar) GCC_ASM_EXPORT (ArmWriteVBar) GCC_ASM_EXPORT (ArmEnableVFP) GCC_ASM_EXPORT (ArmCallWFI) GCC_ASM_EXPORT (ArmReadCbar) -GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) GCC_ASM_EXPORT (ArmReadMpidr) GCC_ASM_EXPORT (ArmReadTpidrurw) GCC_ASM_EXPORT (ArmWriteTpidrurw) GCC_ASM_EXPORT (ArmIsArchTimerImplemented) GCC_ASM_EXPORT (ArmReadIdPfr1) +GCC_ASM_EXPORT (ArmReadIdMmfr0) .set DC_ON, (0x1<<2) .set IC_ON, (0x1<<12) @@ -61,43 +61,31 @@ GCC_ASM_EXPORT (ArmReadIdPfr1) ASM_PFX(ArmInvalidateDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line - dsb - isb + mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line bx lr ASM_PFX(ArmCleanDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c10, 1 @clean single data cache line - dsb - isb + mcr p15, 0, r0, c7, c10, 1 @clean single data cache line bx lr ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line - dsb - isb bx lr ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line - dsb - isb + mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line bx lr ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line - dsb - isb + mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line bx lr ASM_PFX(ArmCleanDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c10, 2 @ Clean this line - dsb - isb + mcr p15, 0, r0, c7, c10, 2 @ Clean this line bx lr ASM_PFX(ArmInvalidateInstructionCache): @@ -139,7 +127,7 @@ ASM_PFX(ArmDisableCachesAndMmu): ASM_PFX(ArmMmuEnabled): mrc p15,0,R0,c1,c0,0 and R0,R0,#1 - bx LR + bx LR ASM_PFX(ArmEnableDataCache): ldr R1,=DC_ON @@ -149,7 +137,7 @@ ASM_PFX(ArmEnableDataCache): dsb isb bx LR - + ASM_PFX(ArmDisableDataCache): ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data @@ -167,7 +155,7 @@ ASM_PFX(ArmEnableInstructionCache): dsb isb bx LR - + ASM_PFX(ArmDisableInstructionCache): ldr R1,=IC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data @@ -209,7 +197,7 @@ ASM_PFX(ArmSetLowVectors): ASM_PFX(ArmSetHighVectors): mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) - orr r0, r0, #0x00002000 @ clear V bit + orr r0, r0, #0x00002000 @ Set V bit mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data) isb bx LR @@ -223,14 +211,14 @@ ASM_PFX(ArmV7AllDataCachesOperation): beq L_Finished mov R10, #0 -Loop1: +Loop1: add R2, R10, R10, LSR #1 @ Work out 3xcachelevel mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level and R12, R12, #7 @ get those 3 bits alone cmp R12, #2 blt L_Skip @ no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb @ isb to sync the change to the CacheSizeID reg + isb @ isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) and R2, R12, #0x7 @ extract the line length field add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) @@ -244,10 +232,10 @@ Loop1: sub R7, R7, #1 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) -Loop2: +Loop2: mov R9, R4 @ R9 working copy of the max way size (right aligned) -Loop3: +Loop3: orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 orr R0, R0, R7, LSL R2 @ factor in the index number @@ -257,11 +245,11 @@ Loop3: bge Loop3 subs R7, R7, #1 @ decrement the index bge Loop2 -L_Skip: +L_Skip: add R10, R10, #2 @ increment the cache number cmp R3, R10 bgt Loop1 - + L_Finished: dsb ldmfd SP!, {r4-r12, lr} @@ -270,19 +258,23 @@ L_Finished: ASM_PFX(ArmDataMemoryBarrier): dmb bx LR - -ASM_PFX(ArmDataSyncronizationBarrier): -ASM_PFX(ArmDrainWriteBuffer): + +ASM_PFX(ArmDataSynchronizationBarrier): dsb bx LR - + ASM_PFX(ArmInstructionSynchronizationBarrier): isb bx LR +ASM_PFX(ArmReadVBar): + # Set the Address of the Vector Table in the VBAR register + mrc p15, 0, r0, c12, c0, 0 + bx lr + ASM_PFX(ArmWriteVBar): # Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 + mcr p15, 0, r0, c12, c0, 0 # Ensure the SCTLR.V bit is clear mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 @ clear V bit @@ -297,6 +289,7 @@ ASM_PFX(ArmEnableVFP): orr r0, r0, #0x00f00000 # Write back CPACR (Coprocessor Access Control Register) mcr p15, 0, r0, c1, c0, 2 + isb # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. mov r0, #0x40000000 mcr p10,#0x7,r0,c8,c0,#0 @@ -311,15 +304,10 @@ ASM_PFX(ArmReadCbar): mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register bx lr -ASM_PFX(ArmInvalidateInstructionAndDataTlb): - mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB - dsb - bx lr - ASM_PFX(ArmReadMpidr): mrc p15, 0, r0, c0, c0, 5 @ read MPIDR bx lr - + ASM_PFX(ArmReadTpidrurw): mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW bx lr @@ -337,4 +325,8 @@ ASM_PFX(ArmReadIdPfr1): mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register bx lr +ASM_PFX(ArmReadIdMmfr0): + mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register + bx lr + ASM_FUNCTION_REMOVE_IF_UNREFERENCED