X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPkg%2FLibrary%2FArmLib%2FArmV7%2FArmV7Support.S;h=c765032c9e4db66dc874dd6714566c05e70c27a0;hb=cf580da1bc4c16026cb1732f741a892b2d3d3d67;hp=d402118ce2ccdc8fe26605cd517416ff90a534a2;hpb=9401d6f4b989d977f8b0aa4946168a92b748aead;p=mirror_edk2.git diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index d402118ce2..c765032c9e 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -1,4 +1,4 @@ -#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ # # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. @@ -18,12 +18,13 @@ GCC_ASM_EXPORT (ArmInvalidateInstructionCache) GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA) GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA) +GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA) GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA) GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay) GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay) GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay) -GCC_ASM_EXPORT (ArmDrainWriteBuffer) GCC_ASM_EXPORT (ArmEnableMmu) GCC_ASM_EXPORT (ArmDisableMmu) GCC_ASM_EXPORT (ArmDisableCachesAndMmu) @@ -38,22 +39,20 @@ GCC_ASM_EXPORT (ArmDisableBranchPrediction) GCC_ASM_EXPORT (ArmSetLowVectors) GCC_ASM_EXPORT (ArmSetHighVectors) GCC_ASM_EXPORT (ArmV7AllDataCachesOperation) -GCC_ASM_EXPORT (ArmV7PerformPoUDataCacheOperation) GCC_ASM_EXPORT (ArmDataMemoryBarrier) -GCC_ASM_EXPORT (ArmDataSyncronizationBarrier) +GCC_ASM_EXPORT (ArmDataSynchronizationBarrier) GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier) GCC_ASM_EXPORT (ArmReadVBar) GCC_ASM_EXPORT (ArmWriteVBar) GCC_ASM_EXPORT (ArmEnableVFP) GCC_ASM_EXPORT (ArmCallWFI) GCC_ASM_EXPORT (ArmReadCbar) -GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb) GCC_ASM_EXPORT (ArmReadMpidr) -GCC_ASM_EXPORT (ArmReadMidr) GCC_ASM_EXPORT (ArmReadTpidrurw) GCC_ASM_EXPORT (ArmWriteTpidrurw) GCC_ASM_EXPORT (ArmIsArchTimerImplemented) GCC_ASM_EXPORT (ArmReadIdPfr1) +GCC_ASM_EXPORT (ArmReadIdMmfr0) .set DC_ON, (0x1<<2) .set IC_ON, (0x1<<12) @@ -64,43 +63,40 @@ GCC_ASM_EXPORT (ArmReadIdPfr1) ASM_PFX(ArmInvalidateDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line - dsb - isb + mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line bx lr ASM_PFX(ArmCleanDataCacheEntryByMVA): - mcr p15, 0, r0, c7, c10, 1 @clean single data cache line - dsb - isb + mcr p15, 0, r0, c7, c10, 1 @clean single data cache line bx lr +ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA): + mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU + bx lr + +ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA): + mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU + mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor + bx lr + ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA): mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line - dsb - isb bx lr ASM_PFX(ArmInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line - dsb - isb + mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line bx lr ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line - dsb - isb + mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line bx lr ASM_PFX(ArmCleanDataCacheEntryBySetWay): - mcr p15, 0, r0, c7, c10, 2 @ Clean this line - dsb - isb + mcr p15, 0, r0, c7, c10, 2 @ Clean this line bx lr ASM_PFX(ArmInvalidateInstructionCache): @@ -142,7 +138,7 @@ ASM_PFX(ArmDisableCachesAndMmu): ASM_PFX(ArmMmuEnabled): mrc p15,0,R0,c1,c0,0 and R0,R0,#1 - bx LR + bx LR ASM_PFX(ArmEnableDataCache): ldr R1,=DC_ON @@ -152,7 +148,7 @@ ASM_PFX(ArmEnableDataCache): dsb isb bx LR - + ASM_PFX(ArmDisableDataCache): ldr R1,=DC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data @@ -170,7 +166,7 @@ ASM_PFX(ArmEnableInstructionCache): dsb isb bx LR - + ASM_PFX(ArmDisableInstructionCache): ldr R1,=IC_ON mrc p15,0,R0,c1,c0,0 @Read control register configuration data @@ -226,14 +222,14 @@ ASM_PFX(ArmV7AllDataCachesOperation): beq L_Finished mov R10, #0 -Loop1: +Loop1: add R2, R10, R10, LSR #1 @ Work out 3xcachelevel mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level and R12, R12, #7 @ get those 3 bits alone cmp R12, #2 blt L_Skip @ no cache or only instruction cache at this level mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb @ isb to sync the change to the CacheSizeID reg + isb @ isb to sync the change to the CacheSizeID reg mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) and R2, R12, #0x7 @ extract the line length field add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) @@ -247,10 +243,10 @@ Loop1: sub R7, R7, #1 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) -Loop2: +Loop2: mov R9, R4 @ R9 working copy of the max way size (right aligned) -Loop3: +Loop3: orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 orr R0, R0, R7, LSL R2 @ factor in the index number @@ -260,61 +256,12 @@ Loop3: bge Loop3 subs R7, R7, #1 @ decrement the index bge Loop2 -L_Skip: +L_Skip: add R10, R10, #2 @ increment the cache number cmp R3, R10 bgt Loop1 - -L_Finished: - dsb - ldmfd SP!, {r4-r12, lr} - bx LR - -ASM_PFX(ArmV7PerformPoUDataCacheOperation): - stmfd SP!,{r4-r12, LR} - mov R1, R0 @ Save Function call in R1 - mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR - ands R3, R6, #0x38000000 @ Mask out all but Level of Unification (LoU) - mov R3, R3, LSR #26 @ Cache level value (naturally aligned) - beq Finished2 - mov R10, #0 -Loop4: - add R2, R10, R10, LSR #1 @ Work out 3xcachelevel - mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level - and R12, R12, #7 @ get those 3 bits alone - cmp R12, #2 - blt Skip2 @ no cache or only instruction cache at this level - mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction - isb @ isb to sync the change to the CacheSizeID reg - mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR) - and R2, R12, #0x7 @ extract the line length field - add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes) - ldr R4, =0x3FF - ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned) - clz R5, R4 @ R5 is the bit position of the way size increment - ldr R7, =0x00007FFF - ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned) - -Loop5: - mov R9, R4 @ R9 working copy of the max way size (right aligned) - -Loop6: - orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11 - orr R0, R0, R7, LSL R2 @ factor in the index number - - blx R1 - - subs R9, R9, #1 @ decrement the way number - bge Loop6 - subs R7, R7, #1 @ decrement the index - bge Loop5 -Skip2: - add R10, R10, #2 @ increment the cache number - cmp R3, R10 - bgt Loop4 - -Finished2: +L_Finished: dsb ldmfd SP!, {r4-r12, lr} bx LR @@ -322,12 +269,11 @@ Finished2: ASM_PFX(ArmDataMemoryBarrier): dmb bx LR - -ASM_PFX(ArmDataSyncronizationBarrier): -ASM_PFX(ArmDrainWriteBuffer): + +ASM_PFX(ArmDataSynchronizationBarrier): dsb bx LR - + ASM_PFX(ArmInstructionSynchronizationBarrier): isb bx LR @@ -339,7 +285,7 @@ ASM_PFX(ArmReadVBar): ASM_PFX(ArmWriteVBar): # Set the Address of the Vector Table in the VBAR register - mcr p15, 0, r0, c12, c0, 0 + mcr p15, 0, r0, c12, c0, 0 # Ensure the SCTLR.V bit is clear mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) bic r0, r0, #0x00002000 @ clear V bit @@ -357,7 +303,11 @@ ASM_PFX(ArmEnableVFP): isb # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally. mov r0, #0x40000000 +#ifndef __clang__ mcr p10,#0x7,r0,c8,c0,#0 +#else + vmsr fpexc, r0 +#endif bx lr ASM_PFX(ArmCallWFI): @@ -369,19 +319,10 @@ ASM_PFX(ArmReadCbar): mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register bx lr -ASM_PFX(ArmInvalidateInstructionAndDataTlb): - mcr p15, 0, r0, c8, c7, 0 @ Invalidate Inst TLB and Data TLB - dsb - bx lr - ASM_PFX(ArmReadMpidr): mrc p15, 0, r0, c0, c0, 5 @ read MPIDR bx lr -ASM_PFX(ArmReadMidr): - mrc p15, 0, r0, c0, c0, 0 @ Read Main ID Register - bx lr - ASM_PFX(ArmReadTpidrurw): mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW bx lr @@ -399,4 +340,8 @@ ASM_PFX(ArmReadIdPfr1): mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register bx lr +ASM_PFX(ArmReadIdMmfr0): + mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register + bx lr + ASM_FUNCTION_REMOVE_IF_UNREFERENCED