X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPlatformPkg%2FArmPlatformPkg.dec;h=2515af8e5918486d014d13f3c7c3fba2fbb5510b;hb=807c26d306fc3d5f8bb3330f280a0f1f00ad964d;hp=b9f38b674700ba1fc2fe52b110856044811727af;hpb=bb5420bb2b5fa146de1ddf2da5932b214e5743a9;p=mirror_edk2.git

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index b9f38b6747..2515af8e59 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -1,6 +1,6 @@
 #/** @file
 #
-#  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
 #
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -42,6 +42,9 @@
 
   gArmBootMonFsFileInfoGuid   = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
 
+  ## Include/Guid/ArmPlatformEvents.h
+  gArmPlatformUpdateFdtEventGuid = { 0xaffe115b, 0x8589, 0x456d, { 0xba, 0xb5, 0x8f, 0x2e, 0xda, 0x53, 0xae, 0xb7 } }
+
 [Ppis]
   ## Include/Ppi/ArmGlobalVariable.h
   gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }
@@ -149,6 +152,68 @@
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
   gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
 
+  #
+  # Inclusive range of allowed PCI buses.
+  #
+  gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
+  gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
+
+  #
+  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
+  # Note that "IO" is just another MMIO range that simulates IO space; there
+  # are no special instructions to access it.
+  #
+  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
+  # specific to their containing address spaces. In order to get the physical
+  # address for the CPU, for a given access, the respective translation value
+  # has to be added.
+  #
+  # The translations always have to be initialized like this, using UINT64:
+  #
+  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
+  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
+  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
+  #
+  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
+  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
+  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
+  #
+  # because (a) the target address space (ie. the cpu-physical space) is
+  # 64-bit, and (b) the translation values are meant as offsets for *modular*
+  # arithmetic.
+  #
+  # Accordingly, the translation itself needs to be implemented as:
+  #
+  #   UINT64 UntranslatedIoAddress;     // input parameter
+  #   UINT32 UntranslatedMmio32Address; // input parameter
+  #   UINT64 UntranslatedMmio64Address; // input parameter
+  #
+  #   UINT64 TranslatedIoAddress;       // output parameter
+  #   UINT64 TranslatedMmio32Address;   // output parameter
+  #   UINT64 TranslatedMmio64Address;   // output parameter
+  #
+  #   TranslatedIoAddress     = UntranslatedIoAddress +
+  #                             PcdPciIoTranslation;
+  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
+  #                             PcdPciMmio32Translation;
+  #   TranslatedMmio64Address = UntranslatedMmio64Address +
+  #                             PcdPciMmio64Translation;
+  #
+  #  The modular arithmetic performed in UINT64 ensures that the translation
+  #  works correctly regardless of the relation between IoCpuBase and
+  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
+  #  PcdPciMmio64Base.
+  #
+  gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
+  gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
+  gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
+  gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
+  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
+  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
+  gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
+
 [PcdsFixedAtBuild.ARM]
   # Stack for CPU Cores in Secure Monitor Mode
   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007