X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPlatformPkg%2FArmPlatformPkg.dec;h=2d82ead7612ae05c6f16f76008bde605a80ae5b9;hb=01df510319f3de8eb358e400dae786cddc160180;hp=2d0627595364ff00010da2b64f116933fc27577d;hpb=91673dfdfe78906023f07e585002689e8baf654e;p=mirror_edk2.git

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec
index 2d06275953..2d82ead761 100644
--- a/ArmPlatformPkg/ArmPlatformPkg.dec
+++ b/ArmPlatformPkg/ArmPlatformPkg.dec
@@ -1,6 +1,6 @@
 #/** @file
 #
-#  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+#  Copyright (c) 2011-2017, ARM Limited. All rights reserved.
 #  Copyright (c) 2015, Intel Corporation. All rights reserved.
 #
 #  This program and the accompanying materials
@@ -55,7 +55,7 @@
   gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
 
   # Enable Legacy Linux support in the BDS
-  gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E
+  gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E
 
 [PcdsFixedAtBuild.common]
   gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
@@ -96,6 +96,13 @@
   gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
   gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
   gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
+  gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F
+  gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E
+
+  ## PL011 Serial Debug UART
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031
+  gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032
 
   ## PL061 GPIO
   gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
@@ -124,67 +131,7 @@
   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
   gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
 
-  #
-  # Inclusive range of allowed PCI buses.
-  #
-  gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
-  gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
-
-  #
-  # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
-  # Note that "IO" is just another MMIO range that simulates IO space; there
-  # are no special instructions to access it.
-  #
-  # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
-  # specific to their containing address spaces. In order to get the physical
-  # address for the CPU, for a given access, the respective translation value
-  # has to be added.
-  #
-  # The translations always have to be initialized like this, using UINT64:
-  #
-  #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
-  #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
-  #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
-  #
-  #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
-  #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
-  #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
-  #
-  # because (a) the target address space (ie. the cpu-physical space) is
-  # 64-bit, and (b) the translation values are meant as offsets for *modular*
-  # arithmetic.
-  #
-  # Accordingly, the translation itself needs to be implemented as:
-  #
-  #   UINT64 UntranslatedIoAddress;     // input parameter
-  #   UINT32 UntranslatedMmio32Address; // input parameter
-  #   UINT64 UntranslatedMmio64Address; // input parameter
-  #
-  #   UINT64 TranslatedIoAddress;       // output parameter
-  #   UINT64 TranslatedMmio32Address;   // output parameter
-  #   UINT64 TranslatedMmio64Address;   // output parameter
-  #
-  #   TranslatedIoAddress     = UntranslatedIoAddress +
-  #                             PcdPciIoTranslation;
-  #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
-  #                             PcdPciMmio32Translation;
-  #   TranslatedMmio64Address = UntranslatedMmio64Address +
-  #                             PcdPciMmio64Translation;
-  #
-  #  The modular arithmetic performed in UINT64 ensures that the translation
-  #  works correctly regardless of the relation between IoCpuBase and
-  #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
-  #  PcdPciMmio64Base.
-  #
-  gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
-  gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
-  gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
-  gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
-  gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
+  gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033
 
 [PcdsFixedAtBuild.ARM]
   # Stack for CPU Cores in Secure Monitor Mode