X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=ArmPlatformPkg%2FPrePeiCore%2FPrePeiCore.c;h=3a81e2e23f2c77b3c20e5244bd8d6d4557b0ec7b;hb=8ee193e898854e27a676ebddb775188e20882a9f;hp=f76a1b191fe5c53a756c0d123d4429d3465af2c0;hpb=80ddb68d41519506e100a1d5028975ddcbc6dd65;p=mirror_edk2.git diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c index f76a1b191f..3a81e2e23f 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -1,89 +1,103 @@ /** @file * Main file supporting the transition to PEI Core in Normal World for Versatile Express * -* Copyright (c) 2011, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php +* Copyright (c) 2011-2014, ARM Limited. All rights reserved. * -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. * **/ -#include -#include -#include -#include -#include #include -#include +#include #include -#include - -EFI_STATUS -EFIAPI -SecTemporaryRamSupport ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, - IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, - IN UINTN CopySize - ); -VOID -SecSwitchStack ( - INTN StackDelta - ); +#include "PrePeiCore.h" -EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPpi = {SecTemporaryRamSupport}; +CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport }; -EFI_PEI_PPI_DESCRIPTOR gSecPpiTable[] = { +CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = { { - EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + EFI_PEI_PPI_DESCRIPTOR_PPI, &gEfiTemporaryRamSupportPpiGuid, - &mSecTemporaryRamSupportPpi + (VOID *) &mTemporaryRamSupportPpi } }; -// Vector Table for Pei Phase -VOID PeiVectorTable (VOID); - +VOID +CreatePpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList; + UINTN PlatformPpiListSize; + UINTN ListBase; + EFI_PEI_PPI_DESCRIPTOR *LastPpi; + + // Get the Platform PPIs + PlatformPpiListSize = 0; + ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList); + + // Copy the Common and Platform PPis in Temporrary Memory + ListBase = PcdGet64 (PcdCPUCoresStackBase); + CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable)); + CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize); + + // Set the Terminate flag on the last PPI entry + LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1; + LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + + *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase; + *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize; +} VOID CEntryPoint ( - IN UINTN CoreId, + IN UINTN MpId, IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint ) { - //Clean Data cache - ArmCleanInvalidateDataCache(); - - //Invalidate instruction cache - ArmInvalidateInstructionCache(); - - // Enable Instruction & Data caches - ArmEnableDataCache(); - ArmEnableInstructionCache(); + // Data Cache enabled on Primary core when MMU is enabled. + ArmDisableDataCache (); + // Invalidate Data cache + ArmInvalidateDataCache (); + // Invalidate instruction cache + ArmInvalidateInstructionCache (); + // Enable Instruction Caches on all cores. + ArmEnableInstructionCache (); // // Note: Doesn't have to Enable CPU interface in non-secure world, // as Non-secure interface is already enabled in Secure world. // - // Write VBAR - The Vector table must be 32-byte aligned - ASSERT(((UINT32)PeiVectorTable & ((1 << 5)-1)) == 0); - ArmWriteVBar((UINT32)PeiVectorTable); + // Write VBAR - The Exception Vector table must be aligned to its requirement + // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure + // 'Align=4K' is defined into your FDF for this module. + ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0); + ArmWriteVBar ((UINTN)PeiVectorTable); //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on. - //If not primary Jump to Secondary Main - if(0 == CoreId) { - //Goto primary Main. - primary_main(PeiCoreEntryPoint); + // If not primary Jump to Secondary Main + if (ArmPlatformIsPrimaryCore (MpId)) { + // Initialize the Debug Agent for Source Level Debugging + InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL); + SaveAndSetDebugTimerInterrupt (TRUE); + + // Initialize the platform specific controllers + ArmPlatformInitialize (MpId); + + // Goto primary Main. + PrimaryMain (PeiCoreEntryPoint); } else { - secondary_main(CoreId); + SecondaryMain (MpId); } // PEI Core should always load and never return @@ -92,65 +106,38 @@ CEntryPoint ( EFI_STATUS EFIAPI -SecTemporaryRamSupport ( +PrePeiCoreTemporaryRamSupport ( IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, IN UINTN CopySize ) { + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + UINTN HeapSize; + + HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT); + + OldHeap = (VOID*)(UINTN)TemporaryMemoryBase; + NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize)); + + OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize); + NewStack = (VOID*)(UINTN)PermanentMemoryBase; + + // + // Migrate the temporary memory stack to permanent memory stack. + // + CopyMem (NewStack, OldStack, CopySize - HeapSize); + + // + // Migrate the temporary memory heap to permanent memory heap. // - // Migrate the whole temporary memory to permenent memory. - // - CopyMem ( - (VOID*)(UINTN)PermanentMemoryBase, - (VOID*)(UINTN)TemporaryMemoryBase, - CopySize - ); + CopyMem (NewHeap, OldHeap, HeapSize); - SecSwitchStack((UINTN)(PermanentMemoryBase - TemporaryMemoryBase)); + SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack); return EFI_SUCCESS; } - -VOID -PeiCommonExceptionEntry ( - IN UINT32 Entry, - IN UINT32 LR - ) -{ - CHAR8 Buffer[100]; - UINTN CharCount; - - switch (Entry) { - case 0: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reset Exception at 0x%X\n\r",LR); - break; - case 1: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Undefined Exception at 0x%X\n\r",LR); - break; - case 2: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"SWI Exception at 0x%X\n\r",LR); - break; - case 3: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"PrefetchAbort Exception at 0x%X\n\r",LR); - break; - case 4: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"DataAbort Exception at 0x%X\n\r",LR); - break; - case 5: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Reserved Exception at 0x%X\n\r",LR); - break; - case 6: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"IRQ Exception at 0x%X\n\r",LR); - break; - case 7: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"FIQ Exception at 0x%X\n\r",LR); - break; - default: - CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Unknown Exception at 0x%X\n\r",LR); - break; - } - SerialPortWrite ((UINT8 *) Buffer, CharCount); - while(1); -}