X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=BaseTools%2FSource%2FC%2FGenFw%2FElf64Convert.c;h=4636cfee03a72fb357f43547ef143874bc054609;hb=f7496d717357b9af78414d19679b073403812340;hp=a3f1f5d3d4c7bdbbc91a394e97a36f88166fd45c;hpb=4f7d5c6792b67ed7b4fd9f8f5f64649f1f41bd95;p=mirror_edk2.git
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index a3f1f5d3d4..4636cfee03 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -1,7 +1,7 @@
/** @file
Elf64 convert solution
-Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.
+Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.
This program and the accompanying materials are licensed and made available
@@ -171,6 +171,10 @@ InitializeElf64 (
//
VerboseMsg ("Create COFF Section Offset Buffer");
mCoffSectionsOffset = (UINT32 *)malloc(mEhdr->e_shnum * sizeof (UINT32));
+ if (mCoffSectionsOffset == NULL) {
+ Error (NULL, 0, 4001, "Resource", "memory cannot be allocated!");
+ return FALSE;
+ }
memset(mCoffSectionsOffset, 0, mEhdr->e_shnum * sizeof(UINT32));
//
@@ -197,8 +201,11 @@ GetShdrByIndex (
UINT32 Num
)
{
- if (Num >= mEhdr->e_shnum)
- return NULL;
+ if (Num >= mEhdr->e_shnum) {
+ Error (NULL, 0, 3000, "Invalid", "GetShdrByIndex: Index %u is too high.", Num);
+ exit(EXIT_FAILURE);
+ }
+
return (Elf_Shdr*)((UINT8*)mShdrBase + Num * mEhdr->e_shentsize);
}
@@ -255,6 +262,66 @@ IsDataShdr (
return (BOOLEAN) (Shdr->sh_flags & (SHF_WRITE | SHF_ALLOC)) == (SHF_ALLOC | SHF_WRITE);
}
+STATIC
+BOOLEAN
+IsStrtabShdr (
+ Elf_Shdr *Shdr
+ )
+{
+ Elf_Shdr *Namedr = GetShdrByIndex(mEhdr->e_shstrndx);
+
+ return (BOOLEAN) (strcmp((CHAR8*)mEhdr + Namedr->sh_offset + Shdr->sh_name, ELF_STRTAB_SECTION_NAME) == 0);
+}
+
+STATIC
+Elf_Shdr *
+FindStrtabShdr (
+ VOID
+ )
+{
+ UINT32 i;
+ for (i = 0; i < mEhdr->e_shnum; i++) {
+ Elf_Shdr *shdr = GetShdrByIndex(i);
+ if (IsStrtabShdr(shdr)) {
+ return shdr;
+ }
+ }
+ return NULL;
+}
+
+STATIC
+const UINT8 *
+GetSymName (
+ Elf_Sym *Sym
+ )
+{
+ Elf_Shdr *StrtabShdr;
+ UINT8 *StrtabContents;
+ BOOLEAN foundEnd;
+ UINT32 i;
+
+ if (Sym->st_name == 0) {
+ return NULL;
+ }
+
+ StrtabShdr = FindStrtabShdr();
+ if (StrtabShdr == NULL) {
+ return NULL;
+ }
+
+ assert(Sym->st_name < StrtabShdr->sh_size);
+
+ StrtabContents = (UINT8*)mEhdr + StrtabShdr->sh_offset;
+
+ foundEnd = FALSE;
+ for (i= Sym->st_name; (i < StrtabShdr->sh_size) && !foundEnd; i++) {
+ foundEnd = (BOOLEAN)(StrtabContents[i] == 0);
+ }
+ assert(foundEnd);
+
+ return StrtabContents + Sym->st_name;
+}
+
//
// Elf functions interface implementation
//
@@ -287,7 +354,7 @@ ScanSections64 (
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
break;
default:
- VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
+ VerboseMsg ("%s unknown e_machine type %hu. Assume X64", mInImageName, mEhdr->e_machine);
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
break;
}
@@ -309,6 +376,15 @@ ScanSections64 (
}
}
+ //
+ // Check if mCoffAlignment is larger than MAX_COFF_ALIGNMENT
+ //
+ if (mCoffAlignment > MAX_COFF_ALIGNMENT) {
+ Error (NULL, 0, 3000, "Invalid", "Section alignment is larger than MAX_COFF_ALIGNMENT.");
+ assert (FALSE);
+ }
+
+
//
// Move the PE/COFF header right before the first section. This will help us
// save space when converting to TE.
@@ -334,12 +410,8 @@ ScanSections64 (
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {
// if the section address is aligned we must align PE/COFF
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {
- // ARM RVCT tools have behavior outside of the ELF specification to try
- // and make images smaller. If sh_addr is not aligned to sh_addralign
- // then the section needs to preserve sh_addr MOD sh_addralign.
- // Normally doing nothing here works great.
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");
}
}
@@ -369,10 +441,7 @@ ScanSections64 (
}
mDebugOffset = DebugRvaAlign(mCoffOffset);
-
- if (mEhdr->e_machine != EM_ARM) {
- mCoffOffset = CoffAlign(mCoffOffset);
- }
+ mCoffOffset = CoffAlign(mCoffOffset);
if (SectionCount > 1 && mOutImageType == FW_EFI_IMAGE) {
Warning (NULL, 0, 0, NULL, "Mulitple sections in %s are merged into 1 text section. Source level debug might not work correctly.", mInImageName);
@@ -392,12 +461,8 @@ ScanSections64 (
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {
// if the section address is aligned we must align PE/COFF
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {
- // ARM RVCT tools have behavior outside of the ELF specification to try
- // and make images smaller. If sh_addr is not aligned to sh_addralign
- // then the section needs to preserve sh_addr MOD sh_addralign.
- // Normally doing nothing here works great.
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");
}
}
@@ -448,12 +513,8 @@ ScanSections64 (
if ((shdr->sh_addr & (shdr->sh_addralign - 1)) == 0) {
// if the section address is aligned we must align PE/COFF
mCoffOffset = (UINT32) ((mCoffOffset + shdr->sh_addralign - 1) & ~(shdr->sh_addralign - 1));
- } else if ((shdr->sh_addr % shdr->sh_addralign) != (mCoffOffset % shdr->sh_addralign)) {
- // ARM RVCT tools have behavior outside of the ELF specification to try
- // and make images smaller. If sh_addr is not aligned to sh_addralign
- // then the section needs to preserve sh_addr MOD sh_addralign.
- // Normally doing nothing here works great.
- Error (NULL, 0, 3000, "Invalid", "Unsupported section alignment.");
+ } else {
+ Error (NULL, 0, 3000, "Invalid", "Section address not aligned to its own alignment.");
}
}
if (shdr->sh_size != 0) {
@@ -473,6 +534,10 @@ ScanSections64 (
// Allocate base Coff file. Will be expanded later for relocations.
//
mCoffFile = (UINT8 *)malloc(mCoffOffset);
+ if (mCoffFile == NULL) {
+ Error (NULL, 0, 4001, "Resource", "memory cannot be allocated!");
+ }
+ assert (mCoffFile != NULL);
memset(mCoffFile, 0, mCoffOffset);
//
@@ -605,6 +670,9 @@ WriteSections64 (
switch (Shdr->sh_type) {
case SHT_PROGBITS:
/* Copy. */
+ if (Shdr->sh_offset + Shdr->sh_size > mFileBufferSize) {
+ return FALSE;
+ }
memcpy(mCoffFile + mCoffSectionsOffset[Idx],
(UINT8*)mEhdr + Shdr->sh_offset,
(size_t) Shdr->sh_size);
@@ -637,6 +705,20 @@ WriteSections64 (
continue;
}
+ //
+ // If this is a ET_DYN (PIE) executable, we will encounter a dynamic SHT_RELA
+ // section that applies to the entire binary, and which will have its section
+ // index set to #0 (which is a NULL section with the SHF_ALLOC bit cleared).
+ //
+ // In the absence of GOT based relocations (which we currently don't support),
+ // this RELA section will contain redundant R_xxx_RELATIVE relocations, one
+ // for every R_xxx_xx64 relocation appearing in the per-section RELA sections.
+ // (i.e., .rela.text and .rela.data)
+ //
+ if (RelShdr->sh_info == 0) {
+ continue;
+ }
+
//
// Relocation section found. Now extract section information that the relocations
// apply to in the ELF data and the new COFF data.
@@ -679,9 +761,18 @@ WriteSections64 (
// header location.
//
if (Sym->st_shndx == SHN_UNDEF
- || Sym->st_shndx == SHN_ABS
- || Sym->st_shndx > mEhdr->e_shnum) {
- Error (NULL, 0, 3000, "Invalid", "%s bad symbol definition.", mInImageName);
+ || Sym->st_shndx >= mEhdr->e_shnum) {
+ const UINT8 *SymName = GetSymName(Sym);
+ if (SymName == NULL) {
+ SymName = (const UINT8 *)"";
+ }
+
+ Error (NULL, 0, 3000, "Invalid",
+ "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
+ "For example, absolute and undefined symbols are not supported.",
+ mInImageName, SymName, Sym->st_value);
+
+ exit(EXIT_FAILURE);
}
SymShdr = GetShdrByIndex(Sym->st_shndx);
@@ -709,35 +800,46 @@ WriteSections64 (
// Absolute relocation.
//
VerboseMsg ("R_X86_64_64");
- VerboseMsg ("Offset: 0x%08X, Addend: 0x%016LX",
- (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
+ VerboseMsg ("Offset: 0x%08X, Addend: 0x%016LX",
+ (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
*(UINT64 *)Targ);
*(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
VerboseMsg ("Relocation: 0x%016LX", *(UINT64*)Targ);
break;
case R_X86_64_32:
VerboseMsg ("R_X86_64_32");
- VerboseMsg ("Offset: 0x%08X, Addend: 0x%08X",
- (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
+ VerboseMsg ("Offset: 0x%08X, Addend: 0x%08X",
+ (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
*(UINT32 *)Targ);
*(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
VerboseMsg ("Relocation: 0x%08X", *(UINT32*)Targ);
break;
case R_X86_64_32S:
VerboseMsg ("R_X86_64_32S");
- VerboseMsg ("Offset: 0x%08X, Addend: 0x%08X",
- (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
+ VerboseMsg ("Offset: 0x%08X, Addend: 0x%08X",
+ (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
*(UINT32 *)Targ);
*(INT32 *)Targ = (INT32)((INT64)(*(INT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
VerboseMsg ("Relocation: 0x%08X", *(UINT32*)Targ);
break;
+
+ case R_X86_64_PLT32:
+ //
+ // Treat R_X86_64_PLT32 relocations as R_X86_64_PC32: this is
+ // possible since we know all code symbol references resolve to
+ // definitions in the same module (UEFI has no shared libraries),
+ // and so there is never a reason to jump via a PLT entry,
+ // allowing us to resolve the reference using the symbol directly.
+ //
+ VerboseMsg ("Treating R_X86_64_PLT32 as R_X86_64_PC32 ...");
+ /* fall through */
case R_X86_64_PC32:
//
// Relative relocation: Symbol - Ip + Addend
//
VerboseMsg ("R_X86_64_PC32");
- VerboseMsg ("Offset: 0x%08X, Addend: 0x%08X",
- (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
+ VerboseMsg ("Offset: 0x%08X, Addend: 0x%08X",
+ (UINT32)(SecOffset + (Rel->r_offset - SecShdr->sh_addr)),
*(UINT32 *)Targ);
*(UINT32 *)Targ = (UINT32) (*(UINT32 *)Targ
+ (mCoffSectionsOffset[Sym->st_shndx] - SymShdr->sh_addr)
@@ -752,26 +854,59 @@ WriteSections64 (
switch (ELF_R_TYPE(Rel->r_info)) {
case R_AARCH64_ADR_PREL_PG_HI21:
- case R_AARCH64_ADD_ABS_LO12_NC:
- case R_AARCH64_LDST8_ABS_LO12_NC:
- case R_AARCH64_LDST16_ABS_LO12_NC:
- case R_AARCH64_LDST32_ABS_LO12_NC:
- case R_AARCH64_LDST64_ABS_LO12_NC:
- case R_AARCH64_LDST128_ABS_LO12_NC:
//
// AArch64 PG_H21 relocations are typically paired with ABS_LO12
// relocations, where a PC-relative reference with +/- 4 GB range is
// split into a relative high part and an absolute low part. Since
// the absolute low part represents the offset into a 4 KB page, we
+ // either have to convert the ADRP into an ADR instruction, or we
+ // need to use a section alignment of at least 4 KB, so that the
+ // binary appears at a correct offset at runtime. In any case, we
// have to make sure that the 4 KB relative offsets of both the
// section containing the reference as well as the section to which
// it refers have not been changed during PE/COFF conversion (i.e.,
// in ScanSections64() above).
//
+ if (mCoffAlignment < 0x1000) {
+ //
+ // Attempt to convert the ADRP into an ADR instruction.
+ // This is only possible if the symbol is within +/- 1 MB.
+ //
+ INT64 Offset;
+
+ // Decode the ADRP instruction
+ Offset = (INT32)((*(UINT32 *)Targ & 0xffffe0) << 8);
+ Offset = (Offset << (6 - 5)) | ((*(UINT32 *)Targ & 0x60000000) >> (29 - 12));
+
+ //
+ // ADRP offset is relative to the previous page boundary,
+ // whereas ADR offset is relative to the instruction itself.
+ // So fix up the offset so it points to the page containing
+ // the symbol.
+ //
+ Offset -= (UINTN)(Targ - mCoffFile) & 0xfff;
+
+ if (Offset < -0x100000 || Offset > 0xfffff) {
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s due to its size (> 1 MB), this module requires 4 KB section alignment.",
+ mInImageName);
+ break;
+ }
+
+ // Re-encode the offset as an ADR instruction
+ *(UINT32 *)Targ &= 0x1000001f;
+ *(UINT32 *)Targ |= ((Offset & 0x1ffffc) << (5 - 2)) | ((Offset & 0x3) << 29);
+ }
+ /* fall through */
+
+ case R_AARCH64_ADD_ABS_LO12_NC:
+ case R_AARCH64_LDST8_ABS_LO12_NC:
+ case R_AARCH64_LDST16_ABS_LO12_NC:
+ case R_AARCH64_LDST32_ABS_LO12_NC:
+ case R_AARCH64_LDST64_ABS_LO12_NC:
+ case R_AARCH64_LDST128_ABS_LO12_NC:
if (((SecShdr->sh_addr ^ SecOffset) & 0xfff) != 0 ||
- ((SymShdr->sh_addr ^ mCoffSectionsOffset[Sym->st_shndx]) & 0xfff) != 0 ||
- mCoffAlignment < 0x1000) {
- Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 small code model requires 4 KB section alignment.",
+ ((SymShdr->sh_addr ^ mCoffSectionsOffset[Sym->st_shndx]) & 0xfff) != 0) {
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s AARCH64 small code model requires identical ELF and PE/COFF section offsets modulo 4 KB.",
mInImageName);
break;
}
@@ -782,6 +917,9 @@ WriteSections64 (
case R_AARCH64_LD_PREL_LO19:
case R_AARCH64_CALL26:
case R_AARCH64_JUMP26:
+ case R_AARCH64_PREL64:
+ case R_AARCH64_PREL32:
+ case R_AARCH64_PREL16:
//
// The GCC toolchains (i.e., binutils) may corrupt section relative
// relocations when emitting relocation sections into fully linked
@@ -845,9 +983,10 @@ WriteRelocations64 (
switch (ELF_R_TYPE(Rel->r_info)) {
case R_X86_64_NONE:
case R_X86_64_PC32:
+ case R_X86_64_PLT32:
break;
case R_X86_64_64:
- VerboseMsg ("EFI_IMAGE_REL_BASED_DIR64 Offset: 0x%08X",
+ VerboseMsg ("EFI_IMAGE_REL_BASED_DIR64 Offset: 0x%08X",
mCoffSectionsOffset[RelShdr->sh_info] + (Rel->r_offset - SecShdr->sh_addr));
CoffAddFixup(
(UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
@@ -856,7 +995,7 @@ WriteRelocations64 (
break;
case R_X86_64_32S:
case R_X86_64_32:
- VerboseMsg ("EFI_IMAGE_REL_BASED_HIGHLOW Offset: 0x%08X",
+ VerboseMsg ("EFI_IMAGE_REL_BASED_HIGHLOW Offset: 0x%08X",
mCoffSectionsOffset[RelShdr->sh_info] + (Rel->r_offset - SecShdr->sh_addr));
CoffAddFixup(
(UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
@@ -870,20 +1009,13 @@ WriteRelocations64 (
switch (ELF_R_TYPE(Rel->r_info)) {
case R_AARCH64_ADR_PREL_LO21:
- break;
-
case R_AARCH64_CONDBR19:
- break;
-
case R_AARCH64_LD_PREL_LO19:
- break;
-
case R_AARCH64_CALL26:
- break;
-
case R_AARCH64_JUMP26:
- break;
-
+ case R_AARCH64_PREL64:
+ case R_AARCH64_PREL32:
+ case R_AARCH64_PREL16:
case R_AARCH64_ADR_PREL_PG_HI21:
case R_AARCH64_ADD_ABS_LO12_NC:
case R_AARCH64_LDST8_ABS_LO12_NC:
@@ -891,6 +1023,12 @@ WriteRelocations64 (
case R_AARCH64_LDST32_ABS_LO12_NC:
case R_AARCH64_LDST64_ABS_LO12_NC:
case R_AARCH64_LDST128_ABS_LO12_NC:
+ //
+ // No fixups are required for relative relocations, provided that
+ // the relative offsets between sections have been preserved in
+ // the ELF to PE/COFF conversion. We have already asserted that
+ // this is the case in WriteSections64 ().
+ //
break;
case R_AARCH64_ABS64:
@@ -969,7 +1107,7 @@ WriteDebug64 (
NtHdr = (EFI_IMAGE_OPTIONAL_HEADER_UNION *)(mCoffFile + mNtHdrOffset);
DataDir = &NtHdr->Pe32Plus.OptionalHeader.DataDirectory[EFI_IMAGE_DIRECTORY_ENTRY_DEBUG];
DataDir->VirtualAddress = mDebugOffset;
- DataDir->Size = Dir->SizeOfData + sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);
+ DataDir->Size = sizeof(EFI_IMAGE_DEBUG_DIRECTORY_ENTRY);
}
STATIC