X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=IntelFsp2Pkg%2FFspSecCore%2FIa32%2FFspApiEntryM.nasm;h=5dada2af54a4412d0d4cbb089546327b63635ee4;hb=6f219bef55f819cb88c86bd7e9b550de4d4345a1;hp=e7261b41cd28be8dabd4af4614b263253f3c5c50;hpb=630df8c86eac64f918aa74f52cbf042db033d3db;p=mirror_edk2.git
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index e7261b41cd..5dada2af54 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -1,7 +1,7 @@
;; @file
; Provide FSP API entry points.
;
-; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent
;;
@@ -32,6 +32,24 @@ struc FSPM_UPD_COMMON
.size:
endstruc
+struc FSPM_UPD_COMMON_FSP24
+ ; FSP_UPD_HEADER {
+ .FspUpdHeader: resd 8
+ ; }
+ ; FSPM_ARCH2_UPD {
+ .Revision: resb 1
+ .Reserved: resb 3
+ .Length resd 1
+ .StackBase: resq 1
+ .StackSize: resq 1
+ .BootLoaderTolumSize: resd 1
+ .BootMode: resd 1
+ .FspEventHandler resq 1
+ .Reserved1: resb 24
+ ; }
+ .size:
+endstruc
+
;
; Following functions will be provided in C
;
@@ -124,12 +142,22 @@ ASM_PFX(FspApiCommonContinue):
pop eax
FspStackSetup:
+ mov ecx, [edx + FSPM_UPD_COMMON.Revision]
+ cmp ecx, 3
+ jae FspmUpdCommon2
+
;
; StackBase = temp memory base, StackSize = temp memory size
;
mov edi, [edx + FSPM_UPD_COMMON.StackBase]
mov ecx, [edx + FSPM_UPD_COMMON.StackSize]
+ jmp ChkFspHeapSize
+
+FspmUpdCommon2:
+ mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]
+ mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]
+ChkFspHeapSize:
;
; Keep using bootloader stack if heap size % is 0
;
@@ -219,7 +247,7 @@ exit:
global ASM_PFX(FspPeiCoreEntryOff)
ASM_PFX(FspPeiCoreEntryOff):
;
- ; This value will be pached by the build script
+ ; This value will be patched by the build script
;
DD 0x12345678