X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=IntelFsp2Pkg%2FInclude%2FFspGlobalData.h;h=697b20ed4ce3febf2d0c581570472f34614d26db;hb=48249243777882d7d89ca0b86c89e355b5f941f3;hp=71033121c4cba3919bf30ede42932ed12247e7c6;hpb=111f2228ddf487b0ac3491e416bb3dcdcfa4f979;p=mirror_edk2.git

diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/FspGlobalData.h
index 71033121c4..697b20ed4c 100644
--- a/IntelFsp2Pkg/Include/FspGlobalData.h
+++ b/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -1,6 +1,6 @@
 /** @file
 
-  Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
 **/
@@ -10,8 +10,9 @@
 
 #include <FspEas.h>
 
-#define FSP_IN_API_MODE       0
-#define FSP_IN_DISPATCH_MODE  1
+#define FSP_IN_API_MODE          0
+#define FSP_IN_DISPATCH_MODE     1
+#define FSP_GLOBAL_DATA_VERSION  1
 
 #pragma pack(1)
 
@@ -23,15 +24,17 @@ typedef enum {
   TempRamExitApiIndex,
   FspSiliconInitApiIndex,
   FspMultiPhaseSiInitApiIndex,
+  FspSmmInitApiIndex,
   FspApiIndexMax
 } FSP_API_INDEX;
 
 typedef struct  {
-  VOID      *DataPtr;
-  UINT32    MicrocodeRegionBase;
-  UINT32    MicrocodeRegionSize;
-  UINT32    CodeRegionBase;
-  UINT32    CodeRegionSize;
+  VOID     *DataPtr;
+  UINTN    MicrocodeRegionBase;
+  UINTN    MicrocodeRegionSize;
+  UINTN    CodeRegionBase;
+  UINTN    CodeRegionSize;
+  UINTN    Reserved;
 } FSP_PLAT_DATA;
 
 #define FSP_GLOBAL_DATA_SIGNATURE        SIGNATURE_32 ('F', 'S', 'P', 'D')
@@ -39,36 +42,57 @@ typedef struct  {
 #define FSP_PERFORMANCE_DATA_TIMER_MASK  0xFFFFFFFFFFFFFF
 
 typedef struct  {
-  UINT32             Signature;
-  UINT8              Version;
-  UINT8              Reserved1[3];
-  UINT32             CoreStack;
-  UINT32             StatusCode;
-  UINT32             Reserved2[8];
+  UINT32    Signature;
+  UINT8     Version;
+  UINT8     Reserved1[3];
+  ///
+  /// Offset 0x08
+  ///
+  UINTN     CoreStack;
+  UINTN     Reserved2;
+  ///
+  /// IA32: Offset 0x10; X64: Offset 0x18
+  ///
+  UINT32    StatusCode;
+  UINT8     ApiIdx;
+  ///
+  /// 0: FSP in API mode; 1: FSP in DISPATCH mode
+  ///
+  UINT8     FspMode;
+  UINT8     OnSeparateStack;
+  UINT8     Reserved3;
+  UINT32    NumberOfPhases;
+  UINT32    PhasesExecuted;
+  UINT32    Reserved4[8];
+  ///
+  /// IA32: Offset 0x40; X64: Offset 0x48
+  /// Start of UINTN and pointer section
+  /// All UINTN and pointer members must be put in this section
+  /// except CoreStack and Reserved2. In addition, the number of
+  /// UINTN and pointer members must be even for natural alignment
+  /// in both IA32 and X64.
+  ///
   FSP_PLAT_DATA      PlatformData;
-  FSP_INFO_HEADER    *FspInfoHeader;
-  VOID               *UpdDataPtr;
   VOID               *TempRamInitUpdPtr;
   VOID               *MemoryInitUpdPtr;
   VOID               *SiliconInitUpdPtr;
-  UINT8              ApiIdx;
-  ///
-  /// 0: FSP in API mode; 1: FSP in DISPATCH mode
-  ///
-  UINT8              FspMode;
-  UINT8              OnSeparateStack;
-  UINT8              Reserved3;
-  UINT32             NumberOfPhases;
-  UINT32             PhasesExecuted;
+  VOID               *SmmInitUpdPtr;
   ///
+  /// IA32: Offset 0x68; X64: Offset 0x98
   /// To store function parameters pointer
   /// so it can be retrieved after stack switched.
   ///
   VOID               *FunctionParameterPtr;
-  UINT8              Reserved4[16];
+  FSP_INFO_HEADER    *FspInfoHeader;
+  VOID               *UpdDataPtr;
+  UINTN              Reserved5;
+  ///
+  /// End of UINTN and pointer section
+  ///
+  UINT8              Reserved6[16];
   UINT32             PerfSig;
   UINT16             PerfLen;
-  UINT16             Reserved5;
+  UINT16             Reserved7;
   UINT32             PerfIdx;
   UINT64             PerfData[32];
 } FSP_GLOBAL_DATA;