X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FEhciDxe%2FEhci.c;h=787bdc13a022f9cffd4a22f103774ccf8bb001ea;hb=b3b1e97b5523ebd9f8e42bc5bf45f4e79418279f;hp=c141803c388071bab53b82cb7c7ade936e588abf;hpb=f01219e875c68e045f1bc755390f5e238ba5a4ad;p=mirror_edk2.git
diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
index c141803c38..787bdc13a0 100644
--- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
@@ -10,7 +10,7 @@
This way avoids the control transfer on a shared port between EHCI and companion host
controller when UHCI gets attached earlier than EHCI and a USB 2.0 device inserts.
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -120,9 +120,22 @@ EhcReset (
USB2_HC_DEV *Ehc;
EFI_TPL OldTpl;
EFI_STATUS Status;
+ UINT32 DbgCtrlStatus;
+
+ Ehc = EHC_FROM_THIS (This);
+
+ if (Ehc->DevicePath != NULL) {
+ //
+ // Report Status Code to indicate reset happens
+ //
+ REPORT_STATUS_CODE_WITH_DEVICE_PATH (
+ EFI_PROGRESS_CODE,
+ (EFI_IO_BUS_USB | EFI_IOB_PC_RESET),
+ Ehc->DevicePath
+ );
+ }
OldTpl = gBS->RaiseTPL (EHC_TPL);
- Ehc = EHC_FROM_THIS (This);
switch (Attributes) {
case EFI_USB_HC_RESET_GLOBAL:
@@ -133,6 +146,14 @@ EhcReset (
//
// Host Controller must be Halt when Reset it
//
+ if (Ehc->DebugPortNum != 0) {
+ DbgCtrlStatus = EhcReadDbgRegister(Ehc, 0);
+ if ((DbgCtrlStatus & (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) == (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) {
+ Status = EFI_SUCCESS;
+ goto ON_EXIT;
+ }
+ }
+
if (!EhcIsHalt (Ehc)) {
Status = EhcHaltHC (Ehc, EHC_GENERIC_TIMEOUT);
@@ -323,6 +344,7 @@ EhcGetRootHubPortStatus (
UINTN Index;
UINTN MapSize;
EFI_STATUS Status;
+ UINT32 DbgCtrlStatus;
if (PortStatus == NULL) {
return EFI_INVALID_PARAMETER;
@@ -344,6 +366,13 @@ EhcGetRootHubPortStatus (
PortStatus->PortStatus = 0;
PortStatus->PortChangeStatus = 0;
+ if ((Ehc->DebugPortNum != 0) && (PortNumber == (Ehc->DebugPortNum - 1))) {
+ DbgCtrlStatus = EhcReadDbgRegister(Ehc, 0);
+ if ((DbgCtrlStatus & (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) == (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) {
+ goto ON_EXIT;
+ }
+ }
+
State = EhcReadOpReg (Ehc, Offset);
//
@@ -1390,11 +1419,135 @@ ON_EXIT:
return Status;
}
+/**
+ Get the usb debug port related information.
+
+ @param Ehc The EHCI device.
+
+ @retval RETURN_SUCCESS Get debug port number, bar and offset successfully.
+ @retval Others The usb host controller does not supported usb debug port capability.
+
+**/
+EFI_STATUS
+EhcGetUsbDebugPortInfo (
+ IN USB2_HC_DEV *Ehc
+ )
+{
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT16 PciStatus;
+ UINT8 CapabilityPtr;
+ UINT8 CapabilityId;
+ UINT16 DebugPort;
+ EFI_STATUS Status;
+
+ ASSERT (Ehc->PciIo != NULL);
+ PciIo = Ehc->PciIo;
+
+ //
+ // Detect if the EHCI host controller support Capaility Pointer.
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_PRIMARY_STATUS_OFFSET,
+ sizeof (UINT16),
+ &PciStatus
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if ((PciStatus & EFI_PCI_STATUS_CAPABILITY) == 0) {
+ //
+ // The Pci Device Doesn't Support Capability Pointer.
+ //
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Get Pointer To Capability List
+ //
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ PCI_CAPBILITY_POINTER_OFFSET,
+ 1,
+ &CapabilityPtr
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Find Capability ID 0xA, Which Is For Debug Port
+ //
+ while (CapabilityPtr != 0) {
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ CapabilityPtr,
+ 1,
+ &CapabilityId
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (CapabilityId == EHC_DEBUG_PORT_CAP_ID) {
+ break;
+ }
+
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint8,
+ CapabilityPtr + 1,
+ 1,
+ &CapabilityPtr
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ }
+
+ //
+ // No Debug Port Capability Found
+ //
+ if (CapabilityPtr == 0) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Get The Base Address Of Debug Port Register In Debug Port Capability Register
+ //
+ Status = PciIo->Pci.Read (
+ Ehc->PciIo,
+ EfiPciIoWidthUint8,
+ CapabilityPtr + 2,
+ sizeof (UINT16),
+ &DebugPort
+ );
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ Ehc->DebugPortOffset = DebugPort & 0x1FFF;
+ Ehc->DebugPortBarNum = (UINT8)((DebugPort >> 13) - 1);
+ Ehc->DebugPortNum = (UINT8)((Ehc->HcStructParams & 0x00F00000) >> 20);
+
+ return EFI_SUCCESS;
+}
+
/**
Create and initialize a USB2_HC_DEV.
@param PciIo The PciIo on this device.
+ @param DevicePath The device path of host controller.
@param OriginalPciAttributes Original PCI attributes.
@return The allocated and initialized USB2_HC_DEV structure if created,
@@ -1403,8 +1556,9 @@ ON_EXIT:
**/
USB2_HC_DEV *
EhcCreateUsb2Hc (
- IN EFI_PCI_IO_PROTOCOL *PciIo,
- IN UINT64 OriginalPciAttributes
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ IN UINT64 OriginalPciAttributes
)
{
USB2_HC_DEV *Ehc;
@@ -1438,6 +1592,7 @@ EhcCreateUsb2Hc (
Ehc->Usb2Hc.MinorRevision = 0x0;
Ehc->PciIo = PciIo;
+ Ehc->DevicePath = DevicePath;
Ehc->OriginalPciAttributes = OriginalPciAttributes;
InitializeListHead (&Ehc->AsyncIntTransfers);
@@ -1455,6 +1610,8 @@ EhcCreateUsb2Hc (
gBS->FreePool (Ehc);
return NULL;
}
+
+ EhcGetUsbDebugPortInfo (Ehc);
//
// Create AsyncRequest Polling Timer
@@ -1541,6 +1698,8 @@ EhcDriverBindingStart (
UINTN EhciBusNumber;
UINTN EhciDeviceNumber;
UINTN EhciFunctionNumber;
+ UINT32 State;
+ EFI_DEVICE_PATH_PROTOCOL *HcDevicePath;
//
// Open the PciIo Protocol, then enable the USB host controller
@@ -1558,6 +1717,19 @@ EhcDriverBindingStart (
return Status;
}
+ //
+ // Open Device Path Protocol for on USB host controller
+ //
+ HcDevicePath = NULL;
+ Status = gBS->OpenProtocol (
+ Controller,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **) &HcDevicePath,
+ This->DriverBindingHandle,
+ Controller,
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL
+ );
+
PciAttributesSaved = FALSE;
//
// Save original PCI attributes
@@ -1699,7 +1871,7 @@ EhcDriverBindingStart (
//
// Create then install USB2_HC_PROTOCOL
//
- Ehc = EhcCreateUsb2Hc (PciIo, OriginalPciAttributes);
+ Ehc = EhcCreateUsb2Hc (PciIo, HcDevicePath, OriginalPciAttributes);
if (Ehc == NULL) {
DEBUG ((EFI_D_ERROR, "EhcDriverBindingStart: failed to create USB2_HC\n"));
@@ -1727,7 +1899,13 @@ EhcDriverBindingStart (
if (FeaturePcdGet (PcdTurnOffUsbLegacySupport)) {
EhcClearLegacySupport (Ehc);
}
- EhcResetHC (Ehc, EHC_RESET_TIMEOUT);
+
+ if (Ehc->DebugPortNum != 0) {
+ State = EhcReadDbgRegister(Ehc, 0);
+ if ((State & (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) != (USB_DEBUG_PORT_IN_USE | USB_DEBUG_PORT_OWNER)) {
+ EhcResetHC (Ehc, EHC_RESET_TIMEOUT);
+ }
+ }
Status = EhcInitHC (Ehc);