X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FEhciDxe%2FEhciReg.c;h=252e3d5fa2dc1f0a9976f33899385afeb5ed6969;hb=f01219e875c68e045f1bc755390f5e238ba5a4ad;hp=eca9b0b2728ba34facc27285d9176e18cfdd414b;hpb=597f4ee21c004a25d77d0417e9de7f6d5f9aace5;p=mirror_edk2.git

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
index eca9b0b272..252e3d5fa2 100644
--- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
@@ -2,8 +2,8 @@
 
   The EHCI register operation routines.
 
-Copyright (c) 2007 - 2009, Intel Corporation
-All rights reserved. This program and the accompanying materials
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials
 are licensed and made available under the terms and conditions of the BSD License
 which accompanies this distribution.  The full text of the license may be found at
 http://opensource.org/licenses/bsd-license.php
@@ -554,8 +554,12 @@ EhcInitHC (
   )
 {
   EFI_STATUS              Status;
+  UINT32                  Index;
 
-  ASSERT (EhcIsHalt (Ehc));
+  // This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.
+  // This ASSERT needs to be removed so the BeagleBoard will boot. When we fix
+  // the USB stack we can put this ASSERT back in
+  // ASSERT (EhcIsHalt (Ehc));
 
   //
   // Allocate the periodic frame and associated memeory
@@ -570,32 +574,36 @@ EhcInitHC (
   if (EFI_ERROR (Status)) {
     return Status;
   }
-  //
-  // 1. Program the CTRLDSSEGMENT register with the high 32 bit addr
-  //
-  EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);
 
   //
-  // 2. Clear USBINTR to disable all the interrupt. UEFI works by polling
+  // 1. Clear USBINTR to disable all the interrupt. UEFI works by polling
   //
   EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);
 
   //
-  // 3. Program periodic frame list, already done in EhcInitSched
-  // 4. Start the Host Controller
+  // 2. Start the Host Controller
   //
   EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);
 
   //
-  // 5. Set all ports routing to EHC
+  // 3. Power up all ports if EHCI has Port Power Control (PPC) support
   //
-  EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);
+  if (Ehc->HcStructParams & HCSP_PPC) {
+    for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {
+      EhcSetOpRegBit (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), PORTSC_POWER);
+    }
+  }
 
   //
   // Wait roothub port power stable
   //
   gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);
 
+  //
+  // 4. Set all ports routing to EHC
+  //
+  EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);
+
   Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);
 
   if (EFI_ERROR (Status)) {