X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FPciBusDxe%2FPciEnumeratorSupport.c;h=adf36a5b77a2d4cd22af98bdec95e92fc1bdd2e6;hb=f00b5d8352ad010dfdb3e7bec67bc6dc9490dd5f;hp=940d8d296108026c5a126b602687f1e6da40f02d;hpb=1ef267831621d709d685c6e65856bdf711ea7b79;p=mirror_edk2.git

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
index 940d8d2961..adf36a5b77 100644
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c
@@ -481,11 +481,11 @@ GatherPpbInfo (
     // if so, it is assumed non-stardard I/O window alignment is supported by this bridge.
     // Per spec, bit 3-1 of I/O Base Register are reserved bits, so its content can't be assumed.
     //
-    Value = Temp ^ (BIT3 | BIT2 | BIT1);
+    Value = (UINT8)(Temp ^ (BIT3 | BIT2 | BIT1));
     PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
     PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value);
     PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp);
-    Value = (Value ^ Temp) & (BIT3 | BIT2 | BIT1);
+    Value = (UINT8)((Value ^ Temp) & (BIT3 | BIT2 | BIT1));
     switch (Value) {
       case BIT3:
         PciIoDevice->BridgeIoAlignment = 0x7FF;