X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdeModulePkg%2FBus%2FPci%2FXhciPei%2FXhciSched.h;h=bbe623279756cdeda93c0c2e96f8f541231cd0c7;hb=1436aea4d5707e672672a11bda72be2c63c936c3;hp=badc57a51b925d5eb50a07ff92f343a472b17a38;hpb=7c7184e201a90a1d2376e615e55e3f4074731468;p=mirror_edk2.git diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h index badc57a51b..bbe6232797 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h @@ -13,62 +13,62 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // // Transfer types, used in URB to identify the transfer type // -#define XHC_CTRL_TRANSFER 0x01 -#define XHC_BULK_TRANSFER 0x02 +#define XHC_CTRL_TRANSFER 0x01 +#define XHC_BULK_TRANSFER 0x02 // // 6.4.6 TRB Types // -#define TRB_TYPE_NORMAL 1 -#define TRB_TYPE_SETUP_STAGE 2 -#define TRB_TYPE_DATA_STAGE 3 -#define TRB_TYPE_STATUS_STAGE 4 -#define TRB_TYPE_ISOCH 5 -#define TRB_TYPE_LINK 6 -#define TRB_TYPE_EVENT_DATA 7 -#define TRB_TYPE_NO_OP 8 -#define TRB_TYPE_EN_SLOT 9 -#define TRB_TYPE_DIS_SLOT 10 -#define TRB_TYPE_ADDRESS_DEV 11 -#define TRB_TYPE_CON_ENDPOINT 12 -#define TRB_TYPE_EVALU_CONTXT 13 -#define TRB_TYPE_RESET_ENDPOINT 14 -#define TRB_TYPE_STOP_ENDPOINT 15 -#define TRB_TYPE_SET_TR_DEQUE 16 -#define TRB_TYPE_RESET_DEV 17 -#define TRB_TYPE_GET_PORT_BANW 21 -#define TRB_TYPE_FORCE_HEADER 22 -#define TRB_TYPE_NO_OP_COMMAND 23 -#define TRB_TYPE_TRANS_EVENT 32 -#define TRB_TYPE_COMMAND_COMPLT_EVENT 33 -#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34 -#define TRB_TYPE_HOST_CONTROLLER_EVENT 37 -#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38 -#define TRB_TYPE_MFINDEX_WRAP_EVENT 39 +#define TRB_TYPE_NORMAL 1 +#define TRB_TYPE_SETUP_STAGE 2 +#define TRB_TYPE_DATA_STAGE 3 +#define TRB_TYPE_STATUS_STAGE 4 +#define TRB_TYPE_ISOCH 5 +#define TRB_TYPE_LINK 6 +#define TRB_TYPE_EVENT_DATA 7 +#define TRB_TYPE_NO_OP 8 +#define TRB_TYPE_EN_SLOT 9 +#define TRB_TYPE_DIS_SLOT 10 +#define TRB_TYPE_ADDRESS_DEV 11 +#define TRB_TYPE_CON_ENDPOINT 12 +#define TRB_TYPE_EVALU_CONTXT 13 +#define TRB_TYPE_RESET_ENDPOINT 14 +#define TRB_TYPE_STOP_ENDPOINT 15 +#define TRB_TYPE_SET_TR_DEQUE 16 +#define TRB_TYPE_RESET_DEV 17 +#define TRB_TYPE_GET_PORT_BANW 21 +#define TRB_TYPE_FORCE_HEADER 22 +#define TRB_TYPE_NO_OP_COMMAND 23 +#define TRB_TYPE_TRANS_EVENT 32 +#define TRB_TYPE_COMMAND_COMPLT_EVENT 33 +#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34 +#define TRB_TYPE_HOST_CONTROLLER_EVENT 37 +#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38 +#define TRB_TYPE_MFINDEX_WRAP_EVENT 39 // // Endpoint Type (EP Type). // -#define ED_NOT_VALID 0 -#define ED_ISOCH_OUT 1 -#define ED_BULK_OUT 2 -#define ED_INTERRUPT_OUT 3 -#define ED_CONTROL_BIDIR 4 -#define ED_ISOCH_IN 5 -#define ED_BULK_IN 6 -#define ED_INTERRUPT_IN 7 +#define ED_NOT_VALID 0 +#define ED_ISOCH_OUT 1 +#define ED_BULK_OUT 2 +#define ED_INTERRUPT_OUT 3 +#define ED_CONTROL_BIDIR 4 +#define ED_ISOCH_IN 5 +#define ED_BULK_IN 6 +#define ED_INTERRUPT_IN 7 // // 6.4.5 TRB Completion Codes // -#define TRB_COMPLETION_INVALID 0 -#define TRB_COMPLETION_SUCCESS 1 -#define TRB_COMPLETION_DATA_BUFFER_ERROR 2 -#define TRB_COMPLETION_BABBLE_ERROR 3 -#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4 -#define TRB_COMPLETION_TRB_ERROR 5 -#define TRB_COMPLETION_STALL_ERROR 6 -#define TRB_COMPLETION_SHORT_PACKET 13 +#define TRB_COMPLETION_INVALID 0 +#define TRB_COMPLETION_SUCCESS 1 +#define TRB_COMPLETION_DATA_BUFFER_ERROR 2 +#define TRB_COMPLETION_BABBLE_ERROR 3 +#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4 +#define TRB_COMPLETION_TRB_ERROR 5 +#define TRB_COMPLETION_STALL_ERROR 6 +#define TRB_COMPLETION_SHORT_PACKET 13 // // The topology string used to present usb device location @@ -77,23 +77,23 @@ typedef struct _USB_DEV_TOPOLOGY { // // The tier concatenation of down stream port. // - UINT32 RouteString:20; + UINT32 RouteString : 20; // // The root port number of the chain. // - UINT32 RootPortNum:8; + UINT32 RootPortNum : 8; // // The Tier the device reside. // - UINT32 TierNum:4; + UINT32 TierNum : 4; } USB_DEV_TOPOLOGY; // // USB Device's RouteChart // typedef union _USB_DEV_ROUTE { - UINT32 Dword; - USB_DEV_TOPOLOGY Route; + UINT32 Dword; + USB_DEV_TOPOLOGY Route; } USB_DEV_ROUTE; // @@ -118,74 +118,74 @@ typedef struct _USB_ENDPOINT { // TRB Template // typedef struct _TRB_TEMPLATE { - UINT32 Parameter1; + UINT32 Parameter1; - UINT32 Parameter2; + UINT32 Parameter2; - UINT32 Status; + UINT32 Status; - UINT32 CycleBit:1; - UINT32 RsvdZ1:9; - UINT32 Type:6; - UINT32 Control:16; + UINT32 CycleBit : 1; + UINT32 RsvdZ1 : 9; + UINT32 Type : 6; + UINT32 Control : 16; } TRB_TEMPLATE; typedef struct _TRANSFER_RING { - VOID *RingSeg0; - UINTN TrbNumber; - TRB_TEMPLATE *RingEnqueue; - TRB_TEMPLATE *RingDequeue; - UINT32 RingPCS; + VOID *RingSeg0; + UINTN TrbNumber; + TRB_TEMPLATE *RingEnqueue; + TRB_TEMPLATE *RingDequeue; + UINT32 RingPCS; } TRANSFER_RING; typedef struct _EVENT_RING { - VOID *ERSTBase; - VOID *EventRingSeg0; - UINTN TrbNumber; - TRB_TEMPLATE *EventRingEnqueue; - TRB_TEMPLATE *EventRingDequeue; - UINT32 EventRingCCS; + VOID *ERSTBase; + VOID *EventRingSeg0; + UINTN TrbNumber; + TRB_TEMPLATE *EventRingEnqueue; + TRB_TEMPLATE *EventRingDequeue; + UINT32 EventRingCCS; } EVENT_RING; -#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R') +#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R') // // URB (Usb Request Block) contains information for all kinds of // usb requests. // typedef struct _URB { - UINT32 Signature; + UINT32 Signature; // // Usb Device URB related information // - USB_ENDPOINT Ep; - EFI_USB_DEVICE_REQUEST *Request; - VOID *Data; - UINTN DataLen; - VOID *DataPhy; - VOID *DataMap; - EFI_ASYNC_USB_TRANSFER_CALLBACK Callback; - VOID *Context; + USB_ENDPOINT Ep; + EFI_USB_DEVICE_REQUEST *Request; + VOID *Data; + UINTN DataLen; + VOID *DataPhy; + VOID *DataMap; + EFI_ASYNC_USB_TRANSFER_CALLBACK Callback; + VOID *Context; // // Execute result // - UINT32 Result; + UINT32 Result; // // completed data length // - UINTN Completed; + UINTN Completed; // // Command/Tranfer Ring info // - TRANSFER_RING *Ring; - TRB_TEMPLATE *TrbStart; - TRB_TEMPLATE *TrbEnd; - UINTN TrbNum; - BOOLEAN StartDone; - BOOLEAN EndDone; - BOOLEAN Finished; - - TRB_TEMPLATE *EvtTrb; + TRANSFER_RING *Ring; + TRB_TEMPLATE *TrbStart; + TRB_TEMPLATE *TrbEnd; + UINTN TrbNum; + BOOLEAN StartDone; + BOOLEAN EndDone; + BOOLEAN Finished; + + TRB_TEMPLATE *EvtTrb; } URB; // @@ -196,11 +196,11 @@ typedef struct _URB { // is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1). // typedef struct _EVENT_RING_SEG_TABLE_ENTRY { - UINT32 PtrLo; - UINT32 PtrHi; - UINT32 RingTrbSize:16; - UINT32 RsvdZ1:16; - UINT32 RsvdZ2; + UINT32 PtrLo; + UINT32 PtrHi; + UINT32 RingTrbSize : 16; + UINT32 RsvdZ1 : 16; + UINT32 RsvdZ2; } EVENT_RING_SEG_TABLE_ENTRY; // @@ -210,25 +210,25 @@ typedef struct _EVENT_RING_SEG_TABLE_ENTRY { // Rings, and to define the Data stage information for Control Transfer Rings. // typedef struct _TRANSFER_TRB_NORMAL { - UINT32 TRBPtrLo; - - UINT32 TRBPtrHi; - - UINT32 Length:17; - UINT32 TDSize:5; - UINT32 IntTarget:10; - - UINT32 CycleBit:1; - UINT32 ENT:1; - UINT32 ISP:1; - UINT32 NS:1; - UINT32 CH:1; - UINT32 IOC:1; - UINT32 IDT:1; - UINT32 RsvdZ1:2; - UINT32 BEI:1; - UINT32 Type:6; - UINT32 RsvdZ2:16; + UINT32 TRBPtrLo; + + UINT32 TRBPtrHi; + + UINT32 Length : 17; + UINT32 TDSize : 5; + UINT32 IntTarget : 10; + + UINT32 CycleBit : 1; + UINT32 ENT : 1; + UINT32 ISP : 1; + UINT32 NS : 1; + UINT32 CH : 1; + UINT32 IOC : 1; + UINT32 IDT : 1; + UINT32 RsvdZ1 : 2; + UINT32 BEI : 1; + UINT32 Type : 6; + UINT32 RsvdZ2 : 16; } TRANSFER_TRB_NORMAL; // @@ -236,25 +236,25 @@ typedef struct _TRANSFER_TRB_NORMAL { // A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint. // typedef struct _TRANSFER_TRB_CONTROL_SETUP { - UINT32 bmRequestType:8; - UINT32 bRequest:8; - UINT32 wValue:16; - - UINT32 wIndex:16; - UINT32 wLength:16; - - UINT32 Length:17; - UINT32 RsvdZ1:5; - UINT32 IntTarget:10; - - UINT32 CycleBit:1; - UINT32 RsvdZ2:4; - UINT32 IOC:1; - UINT32 IDT:1; - UINT32 RsvdZ3:3; - UINT32 Type:6; - UINT32 TRT:2; - UINT32 RsvdZ4:14; + UINT32 bmRequestType : 8; + UINT32 bRequest : 8; + UINT32 wValue : 16; + + UINT32 wIndex : 16; + UINT32 wLength : 16; + + UINT32 Length : 17; + UINT32 RsvdZ1 : 5; + UINT32 IntTarget : 10; + + UINT32 CycleBit : 1; + UINT32 RsvdZ2 : 4; + UINT32 IOC : 1; + UINT32 IDT : 1; + UINT32 RsvdZ3 : 3; + UINT32 Type : 6; + UINT32 TRT : 2; + UINT32 RsvdZ4 : 14; } TRANSFER_TRB_CONTROL_SETUP; // @@ -262,25 +262,25 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer. // typedef struct _TRANSFER_TRB_CONTROL_DATA { - UINT32 TRBPtrLo; - - UINT32 TRBPtrHi; - - UINT32 Length:17; - UINT32 TDSize:5; - UINT32 IntTarget:10; - - UINT32 CycleBit:1; - UINT32 ENT:1; - UINT32 ISP:1; - UINT32 NS:1; - UINT32 CH:1; - UINT32 IOC:1; - UINT32 IDT:1; - UINT32 RsvdZ1:3; - UINT32 Type:6; - UINT32 DIR:1; - UINT32 RsvdZ2:15; + UINT32 TRBPtrLo; + + UINT32 TRBPtrHi; + + UINT32 Length : 17; + UINT32 TDSize : 5; + UINT32 IntTarget : 10; + + UINT32 CycleBit : 1; + UINT32 ENT : 1; + UINT32 ISP : 1; + UINT32 NS : 1; + UINT32 CH : 1; + UINT32 IOC : 1; + UINT32 IDT : 1; + UINT32 RsvdZ1 : 3; + UINT32 Type : 6; + UINT32 DIR : 1; + UINT32 RsvdZ2 : 15; } TRANSFER_TRB_CONTROL_DATA; // @@ -288,21 +288,21 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA { // A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer. // typedef struct _TRANSFER_TRB_CONTROL_STATUS { - UINT32 RsvdZ1; - UINT32 RsvdZ2; - - UINT32 RsvdZ3:22; - UINT32 IntTarget:10; - - UINT32 CycleBit:1; - UINT32 ENT:1; - UINT32 RsvdZ4:2; - UINT32 CH:1; - UINT32 IOC:1; - UINT32 RsvdZ5:4; - UINT32 Type:6; - UINT32 DIR:1; - UINT32 RsvdZ6:15; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + + UINT32 RsvdZ3 : 22; + UINT32 IntTarget : 10; + + UINT32 CycleBit : 1; + UINT32 ENT : 1; + UINT32 RsvdZ4 : 2; + UINT32 CH : 1; + UINT32 IOC : 1; + UINT32 RsvdZ5 : 4; + UINT32 Type : 6; + UINT32 DIR : 1; + UINT32 RsvdZ6 : 15; } TRANSFER_TRB_CONTROL_STATUS; // @@ -311,21 +311,21 @@ typedef struct _TRANSFER_TRB_CONTROL_STATUS { // for more information on the use and operation of Transfer Events. // typedef struct _EVT_TRB_TRANSFER { - UINT32 TRBPtrLo; + UINT32 TRBPtrLo; - UINT32 TRBPtrHi; + UINT32 TRBPtrHi; - UINT32 Length:24; - UINT32 Completecode:8; + UINT32 Length : 24; + UINT32 Completecode : 8; - UINT32 CycleBit:1; - UINT32 RsvdZ1:1; - UINT32 ED:1; - UINT32 RsvdZ2:7; - UINT32 Type:6; - UINT32 EndpointId:5; - UINT32 RsvdZ3:3; - UINT32 SlotId:8; + UINT32 CycleBit : 1; + UINT32 RsvdZ1 : 1; + UINT32 ED : 1; + UINT32 RsvdZ2 : 7; + UINT32 Type : 6; + UINT32 EndpointId : 5; + UINT32 RsvdZ3 : 3; + UINT32 SlotId : 8; } EVT_TRB_TRANSFER; // @@ -334,26 +334,26 @@ typedef struct _EVT_TRB_TRANSFER { // Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events. // typedef struct _EVT_TRB_COMMAND_COMPLETION { - UINT32 TRBPtrLo; + UINT32 TRBPtrLo; - UINT32 TRBPtrHi; + UINT32 TRBPtrHi; - UINT32 RsvdZ2:24; - UINT32 Completecode:8; + UINT32 RsvdZ2 : 24; + UINT32 Completecode : 8; - UINT32 CycleBit:1; - UINT32 RsvdZ3:9; - UINT32 Type:6; - UINT32 VFID:8; - UINT32 SlotId:8; + UINT32 CycleBit : 1; + UINT32 RsvdZ3 : 9; + UINT32 Type : 6; + UINT32 VFID : 8; + UINT32 SlotId : 8; } EVT_TRB_COMMAND_COMPLETION; typedef union _TRB { - TRB_TEMPLATE TrbTemplate; - TRANSFER_TRB_NORMAL TrbNormal; - TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup; - TRANSFER_TRB_CONTROL_DATA TrbCtrData; - TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus; + TRB_TEMPLATE TrbTemplate; + TRANSFER_TRB_NORMAL TrbNormal; + TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup; + TRANSFER_TRB_CONTROL_DATA TrbCtrData; + TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus; } TRB; // @@ -362,14 +362,14 @@ typedef union _TRB { // mechanisms offered by the xHCI. // typedef struct _CMD_TRB_NO_OP { - UINT32 RsvdZ0; - UINT32 RsvdZ1; - UINT32 RsvdZ2; - - UINT32 CycleBit:1; - UINT32 RsvdZ3:9; - UINT32 Type:6; - UINT32 RsvdZ4:16; + UINT32 RsvdZ0; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + + UINT32 CycleBit : 1; + UINT32 RsvdZ3 : 9; + UINT32 Type : 6; + UINT32 RsvdZ4 : 16; } CMD_TRB_NO_OP; // @@ -378,14 +378,14 @@ typedef struct _CMD_TRB_NO_OP { // selected slot to the host in a Command Completion Event. // typedef struct _CMD_TRB_ENABLE_SLOT { - UINT32 RsvdZ0; - UINT32 RsvdZ1; - UINT32 RsvdZ2; - - UINT32 CycleBit:1; - UINT32 RsvdZ3:9; - UINT32 Type:6; - UINT32 RsvdZ4:16; + UINT32 RsvdZ0; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + + UINT32 CycleBit : 1; + UINT32 RsvdZ3 : 9; + UINT32 Type : 6; + UINT32 RsvdZ4 : 16; } CMD_TRB_ENABLE_SLOT; // @@ -394,15 +394,15 @@ typedef struct _CMD_TRB_ENABLE_SLOT { // internal xHC resources assigned to the slot. // typedef struct _CMD_TRB_DISABLE_SLOT { - UINT32 RsvdZ0; - UINT32 RsvdZ1; - UINT32 RsvdZ2; - - UINT32 CycleBit:1; - UINT32 RsvdZ3:9; - UINT32 Type:6; - UINT32 RsvdZ4:8; - UINT32 SlotId:8; + UINT32 RsvdZ0; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + + UINT32 CycleBit : 1; + UINT32 RsvdZ3 : 9; + UINT32 Type : 6; + UINT32 RsvdZ4 : 8; + UINT32 SlotId : 8; } CMD_TRB_DISABLE_SLOT; // @@ -412,18 +412,18 @@ typedef struct _CMD_TRB_DISABLE_SLOT { // issue a SET_ADDRESS request to the USB device. // typedef struct _CMD_TRB_ADDRESS_DEVICE { - UINT32 PtrLo; + UINT32 PtrLo; - UINT32 PtrHi; + UINT32 PtrHi; - UINT32 RsvdZ1; + UINT32 RsvdZ1; - UINT32 CycleBit:1; - UINT32 RsvdZ2:8; - UINT32 BSR:1; - UINT32 Type:6; - UINT32 RsvdZ3:8; - UINT32 SlotId:8; + UINT32 CycleBit : 1; + UINT32 RsvdZ2 : 8; + UINT32 BSR : 1; + UINT32 Type : 6; + UINT32 RsvdZ3 : 8; + UINT32 SlotId : 8; } CMD_TRB_ADDRESS_DEVICE; // @@ -432,18 +432,18 @@ typedef struct _CMD_TRB_ADDRESS_DEVICE { // endpoints selected by the command. // typedef struct _CMD_TRB_CONFIG_ENDPOINT { - UINT32 PtrLo; + UINT32 PtrLo; - UINT32 PtrHi; + UINT32 PtrHi; - UINT32 RsvdZ1; + UINT32 RsvdZ1; - UINT32 CycleBit:1; - UINT32 RsvdZ2:8; - UINT32 DC:1; - UINT32 Type:6; - UINT32 RsvdZ3:8; - UINT32 SlotId:8; + UINT32 CycleBit : 1; + UINT32 RsvdZ2 : 8; + UINT32 DC : 1; + UINT32 Type : 6; + UINT32 RsvdZ3 : 8; + UINT32 SlotId : 8; } CMD_TRB_CONFIG_ENDPOINT; // @@ -453,17 +453,17 @@ typedef struct _CMD_TRB_CONFIG_ENDPOINT { // shall evaluate any changes // typedef struct _CMD_TRB_EVALUATE_CONTEXT { - UINT32 PtrLo; + UINT32 PtrLo; - UINT32 PtrHi; + UINT32 PtrHi; - UINT32 RsvdZ1; + UINT32 RsvdZ1; - UINT32 CycleBit:1; - UINT32 RsvdZ2:9; - UINT32 Type:6; - UINT32 RsvdZ3:8; - UINT32 SlotId:8; + UINT32 CycleBit : 1; + UINT32 RsvdZ2 : 9; + UINT32 Type : 6; + UINT32 RsvdZ3 : 8; + UINT32 SlotId : 8; } CMD_TRB_EVALUATE_CONTEXT; // @@ -471,17 +471,17 @@ typedef struct _CMD_TRB_EVALUATE_CONTEXT { // The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring // typedef struct _CMD_TRB_RESET_ENDPOINT { - UINT32 RsvdZ0; - UINT32 RsvdZ1; - UINT32 RsvdZ2; - - UINT32 CycleBit:1; - UINT32 RsvdZ3:8; - UINT32 TSP:1; - UINT32 Type:6; - UINT32 EDID:5; - UINT32 RsvdZ4:3; - UINT32 SlotId:8; + UINT32 RsvdZ0; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + + UINT32 CycleBit : 1; + UINT32 RsvdZ3 : 8; + UINT32 TSP : 1; + UINT32 Type : 6; + UINT32 EDID : 5; + UINT32 RsvdZ4 : 3; + UINT32 SlotId : 8; } CMD_TRB_RESET_ENDPOINT; // @@ -490,17 +490,17 @@ typedef struct _CMD_TRB_RESET_ENDPOINT { // Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC. // typedef struct _CMD_TRB_STOP_ENDPOINT { - UINT32 RsvdZ0; - UINT32 RsvdZ1; - UINT32 RsvdZ2; - - UINT32 CycleBit:1; - UINT32 RsvdZ3:9; - UINT32 Type:6; - UINT32 EDID:5; - UINT32 RsvdZ4:2; - UINT32 SP:1; - UINT32 SlotId:8; + UINT32 RsvdZ0; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + + UINT32 CycleBit : 1; + UINT32 RsvdZ3 : 9; + UINT32 Type : 6; + UINT32 EDID : 5; + UINT32 RsvdZ4 : 2; + UINT32 SP : 1; + UINT32 SlotId : 8; } CMD_TRB_STOP_ENDPOINT; // @@ -509,19 +509,19 @@ typedef struct _CMD_TRB_STOP_ENDPOINT { // Pointer and DCS fields of an Endpoint or Stream Context. // typedef struct _CMD_SET_TR_DEQ_POINTER { - UINT32 PtrLo; + UINT32 PtrLo; - UINT32 PtrHi; + UINT32 PtrHi; - UINT32 RsvdZ1:16; - UINT32 StreamID:16; + UINT32 RsvdZ1 : 16; + UINT32 StreamID : 16; - UINT32 CycleBit:1; - UINT32 RsvdZ2:9; - UINT32 Type:6; - UINT32 Endpoint:5; - UINT32 RsvdZ3:3; - UINT32 SlotId:8; + UINT32 CycleBit : 1; + UINT32 RsvdZ2 : 9; + UINT32 Type : 6; + UINT32 Endpoint : 5; + UINT32 RsvdZ3 : 3; + UINT32 SlotId : 8; } CMD_SET_TR_DEQ_POINTER; // @@ -529,226 +529,222 @@ typedef struct _CMD_SET_TR_DEQ_POINTER { // A Link TRB provides support for non-contiguous TRB Rings. // typedef struct _LINK_TRB { - UINT32 PtrLo; + UINT32 PtrLo; - UINT32 PtrHi; + UINT32 PtrHi; - UINT32 RsvdZ1:22; - UINT32 InterTarget:10; + UINT32 RsvdZ1 : 22; + UINT32 InterTarget : 10; - UINT32 CycleBit:1; - UINT32 TC:1; - UINT32 RsvdZ2:2; - UINT32 CH:1; - UINT32 IOC:1; - UINT32 RsvdZ3:4; - UINT32 Type:6; - UINT32 RsvdZ4:16; + UINT32 CycleBit : 1; + UINT32 TC : 1; + UINT32 RsvdZ2 : 2; + UINT32 CH : 1; + UINT32 IOC : 1; + UINT32 RsvdZ3 : 4; + UINT32 Type : 6; + UINT32 RsvdZ4 : 16; } LINK_TRB; // // 6.2.2 Slot Context // typedef struct _SLOT_CONTEXT { - UINT32 RouteString:20; - UINT32 Speed:4; - UINT32 RsvdZ1:1; - UINT32 MTT:1; - UINT32 Hub:1; - UINT32 ContextEntries:5; - - UINT32 MaxExitLatency:16; - UINT32 RootHubPortNum:8; - UINT32 PortNum:8; - - UINT32 TTHubSlotId:8; - UINT32 TTPortNum:8; - UINT32 TTT:2; - UINT32 RsvdZ2:4; - UINT32 InterTarget:10; - - UINT32 DeviceAddress:8; - UINT32 RsvdZ3:19; - UINT32 SlotState:5; - - UINT32 RsvdZ4; - UINT32 RsvdZ5; - UINT32 RsvdZ6; - UINT32 RsvdZ7; + UINT32 RouteString : 20; + UINT32 Speed : 4; + UINT32 RsvdZ1 : 1; + UINT32 MTT : 1; + UINT32 Hub : 1; + UINT32 ContextEntries : 5; + + UINT32 MaxExitLatency : 16; + UINT32 RootHubPortNum : 8; + UINT32 PortNum : 8; + + UINT32 TTHubSlotId : 8; + UINT32 TTPortNum : 8; + UINT32 TTT : 2; + UINT32 RsvdZ2 : 4; + UINT32 InterTarget : 10; + + UINT32 DeviceAddress : 8; + UINT32 RsvdZ3 : 19; + UINT32 SlotState : 5; + + UINT32 RsvdZ4; + UINT32 RsvdZ5; + UINT32 RsvdZ6; + UINT32 RsvdZ7; } SLOT_CONTEXT; typedef struct _SLOT_CONTEXT_64 { - UINT32 RouteString:20; - UINT32 Speed:4; - UINT32 RsvdZ1:1; - UINT32 MTT:1; - UINT32 Hub:1; - UINT32 ContextEntries:5; - - UINT32 MaxExitLatency:16; - UINT32 RootHubPortNum:8; - UINT32 PortNum:8; - - UINT32 TTHubSlotId:8; - UINT32 TTPortNum:8; - UINT32 TTT:2; - UINT32 RsvdZ2:4; - UINT32 InterTarget:10; - - UINT32 DeviceAddress:8; - UINT32 RsvdZ3:19; - UINT32 SlotState:5; - - UINT32 RsvdZ4; - UINT32 RsvdZ5; - UINT32 RsvdZ6; - UINT32 RsvdZ7; - - UINT32 RsvdZ8; - UINT32 RsvdZ9; - UINT32 RsvdZ10; - UINT32 RsvdZ11; - - UINT32 RsvdZ12; - UINT32 RsvdZ13; - UINT32 RsvdZ14; - UINT32 RsvdZ15; - + UINT32 RouteString : 20; + UINT32 Speed : 4; + UINT32 RsvdZ1 : 1; + UINT32 MTT : 1; + UINT32 Hub : 1; + UINT32 ContextEntries : 5; + + UINT32 MaxExitLatency : 16; + UINT32 RootHubPortNum : 8; + UINT32 PortNum : 8; + + UINT32 TTHubSlotId : 8; + UINT32 TTPortNum : 8; + UINT32 TTT : 2; + UINT32 RsvdZ2 : 4; + UINT32 InterTarget : 10; + + UINT32 DeviceAddress : 8; + UINT32 RsvdZ3 : 19; + UINT32 SlotState : 5; + + UINT32 RsvdZ4; + UINT32 RsvdZ5; + UINT32 RsvdZ6; + UINT32 RsvdZ7; + + UINT32 RsvdZ8; + UINT32 RsvdZ9; + UINT32 RsvdZ10; + UINT32 RsvdZ11; + + UINT32 RsvdZ12; + UINT32 RsvdZ13; + UINT32 RsvdZ14; + UINT32 RsvdZ15; } SLOT_CONTEXT_64; - // // 6.2.3 Endpoint Context // typedef struct _ENDPOINT_CONTEXT { - UINT32 EPState:3; - UINT32 RsvdZ1:5; - UINT32 Mult:2; - UINT32 MaxPStreams:5; - UINT32 LSA:1; - UINT32 Interval:8; - UINT32 RsvdZ2:8; - - UINT32 RsvdZ3:1; - UINT32 CErr:2; - UINT32 EPType:3; - UINT32 RsvdZ4:1; - UINT32 HID:1; - UINT32 MaxBurstSize:8; - UINT32 MaxPacketSize:16; - - UINT32 PtrLo; - - UINT32 PtrHi; - - UINT32 AverageTRBLength:16; - UINT32 MaxESITPayload:16; - - UINT32 RsvdZ5; - UINT32 RsvdZ6; - UINT32 RsvdZ7; + UINT32 EPState : 3; + UINT32 RsvdZ1 : 5; + UINT32 Mult : 2; + UINT32 MaxPStreams : 5; + UINT32 LSA : 1; + UINT32 Interval : 8; + UINT32 RsvdZ2 : 8; + + UINT32 RsvdZ3 : 1; + UINT32 CErr : 2; + UINT32 EPType : 3; + UINT32 RsvdZ4 : 1; + UINT32 HID : 1; + UINT32 MaxBurstSize : 8; + UINT32 MaxPacketSize : 16; + + UINT32 PtrLo; + + UINT32 PtrHi; + + UINT32 AverageTRBLength : 16; + UINT32 MaxESITPayload : 16; + + UINT32 RsvdZ5; + UINT32 RsvdZ6; + UINT32 RsvdZ7; } ENDPOINT_CONTEXT; typedef struct _ENDPOINT_CONTEXT_64 { - UINT32 EPState:3; - UINT32 RsvdZ1:5; - UINT32 Mult:2; - UINT32 MaxPStreams:5; - UINT32 LSA:1; - UINT32 Interval:8; - UINT32 RsvdZ2:8; - - UINT32 RsvdZ3:1; - UINT32 CErr:2; - UINT32 EPType:3; - UINT32 RsvdZ4:1; - UINT32 HID:1; - UINT32 MaxBurstSize:8; - UINT32 MaxPacketSize:16; - - UINT32 PtrLo; - - UINT32 PtrHi; - - UINT32 AverageTRBLength:16; - UINT32 MaxESITPayload:16; - - UINT32 RsvdZ5; - UINT32 RsvdZ6; - UINT32 RsvdZ7; - - UINT32 RsvdZ8; - UINT32 RsvdZ9; - UINT32 RsvdZ10; - UINT32 RsvdZ11; - - UINT32 RsvdZ12; - UINT32 RsvdZ13; - UINT32 RsvdZ14; - UINT32 RsvdZ15; - + UINT32 EPState : 3; + UINT32 RsvdZ1 : 5; + UINT32 Mult : 2; + UINT32 MaxPStreams : 5; + UINT32 LSA : 1; + UINT32 Interval : 8; + UINT32 RsvdZ2 : 8; + + UINT32 RsvdZ3 : 1; + UINT32 CErr : 2; + UINT32 EPType : 3; + UINT32 RsvdZ4 : 1; + UINT32 HID : 1; + UINT32 MaxBurstSize : 8; + UINT32 MaxPacketSize : 16; + + UINT32 PtrLo; + + UINT32 PtrHi; + + UINT32 AverageTRBLength : 16; + UINT32 MaxESITPayload : 16; + + UINT32 RsvdZ5; + UINT32 RsvdZ6; + UINT32 RsvdZ7; + + UINT32 RsvdZ8; + UINT32 RsvdZ9; + UINT32 RsvdZ10; + UINT32 RsvdZ11; + + UINT32 RsvdZ12; + UINT32 RsvdZ13; + UINT32 RsvdZ14; + UINT32 RsvdZ15; } ENDPOINT_CONTEXT_64; - // // 6.2.5.1 Input Control Context // typedef struct _INPUT_CONTRL_CONTEXT { - UINT32 Dword1; - UINT32 Dword2; - UINT32 RsvdZ1; - UINT32 RsvdZ2; - UINT32 RsvdZ3; - UINT32 RsvdZ4; - UINT32 RsvdZ5; - UINT32 RsvdZ6; + UINT32 Dword1; + UINT32 Dword2; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + UINT32 RsvdZ3; + UINT32 RsvdZ4; + UINT32 RsvdZ5; + UINT32 RsvdZ6; } INPUT_CONTRL_CONTEXT; typedef struct _INPUT_CONTRL_CONTEXT_64 { - UINT32 Dword1; - UINT32 Dword2; - UINT32 RsvdZ1; - UINT32 RsvdZ2; - UINT32 RsvdZ3; - UINT32 RsvdZ4; - UINT32 RsvdZ5; - UINT32 RsvdZ6; - UINT32 RsvdZ7; - UINT32 RsvdZ8; - UINT32 RsvdZ9; - UINT32 RsvdZ10; - UINT32 RsvdZ11; - UINT32 RsvdZ12; - UINT32 RsvdZ13; - UINT32 RsvdZ14; + UINT32 Dword1; + UINT32 Dword2; + UINT32 RsvdZ1; + UINT32 RsvdZ2; + UINT32 RsvdZ3; + UINT32 RsvdZ4; + UINT32 RsvdZ5; + UINT32 RsvdZ6; + UINT32 RsvdZ7; + UINT32 RsvdZ8; + UINT32 RsvdZ9; + UINT32 RsvdZ10; + UINT32 RsvdZ11; + UINT32 RsvdZ12; + UINT32 RsvdZ13; + UINT32 RsvdZ14; } INPUT_CONTRL_CONTEXT_64; // // 6.2.1 Device Context // typedef struct _DEVICE_CONTEXT { - SLOT_CONTEXT Slot; - ENDPOINT_CONTEXT EP[31]; + SLOT_CONTEXT Slot; + ENDPOINT_CONTEXT EP[31]; } DEVICE_CONTEXT; typedef struct _DEVICE_CONTEXT_64 { - SLOT_CONTEXT_64 Slot; - ENDPOINT_CONTEXT_64 EP[31]; + SLOT_CONTEXT_64 Slot; + ENDPOINT_CONTEXT_64 EP[31]; } DEVICE_CONTEXT_64; // // 6.2.5 Input Context // typedef struct _INPUT_CONTEXT { - INPUT_CONTRL_CONTEXT InputControlContext; - SLOT_CONTEXT Slot; - ENDPOINT_CONTEXT EP[31]; + INPUT_CONTRL_CONTEXT InputControlContext; + SLOT_CONTEXT Slot; + ENDPOINT_CONTEXT EP[31]; } INPUT_CONTEXT; typedef struct _INPUT_CONTEXT_64 { - INPUT_CONTRL_CONTEXT_64 InputControlContext; - SLOT_CONTEXT_64 Slot; - ENDPOINT_CONTEXT_64 EP[31]; + INPUT_CONTRL_CONTEXT_64 InputControlContext; + SLOT_CONTEXT_64 Slot; + ENDPOINT_CONTEXT_64 EP[31]; } INPUT_CONTEXT_64; /** @@ -766,10 +762,10 @@ typedef struct _INPUT_CONTEXT_64 { **/ EFI_STATUS XhcPeiExecTransfer ( - IN PEI_XHC_DEV *Xhc, - IN BOOLEAN CmdTransfer, - IN URB *Urb, - IN UINTN Timeout + IN PEI_XHC_DEV *Xhc, + IN BOOLEAN CmdTransfer, + IN URB *Urb, + IN UINTN Timeout ); /** @@ -783,8 +779,8 @@ XhcPeiExecTransfer ( **/ UINT8 XhcPeiBusDevAddrToSlotId ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 BusDevAddr + IN PEI_XHC_DEV *Xhc, + IN UINT8 BusDevAddr ); /** @@ -798,8 +794,8 @@ XhcPeiBusDevAddrToSlotId ( **/ UINT8 XhcPeiRouteStringToSlotId ( - IN PEI_XHC_DEV *Xhc, - IN USB_DEV_ROUTE RouteString + IN PEI_XHC_DEV *Xhc, + IN USB_DEV_ROUTE RouteString ); /** @@ -813,8 +809,8 @@ XhcPeiRouteStringToSlotId ( **/ UINT8 XhcPeiEndpointToDci ( - IN UINT8 EpAddr, - IN EFI_USB_DATA_DIRECTION Direction + IN UINT8 EpAddr, + IN EFI_USB_DATA_DIRECTION Direction ); /** @@ -827,9 +823,9 @@ XhcPeiEndpointToDci ( **/ VOID XhcPeiRingDoorBell ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 Dci + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 Dci ); /** @@ -846,10 +842,10 @@ XhcPeiRingDoorBell ( **/ EFI_STATUS XhcPeiPollPortStatusChange ( - IN PEI_XHC_DEV *Xhc, - IN USB_DEV_ROUTE ParentRouteChart, - IN UINT8 Port, - IN EFI_USB_PORT_STATUS *PortState + IN PEI_XHC_DEV *Xhc, + IN USB_DEV_ROUTE ParentRouteChart, + IN UINT8 Port, + IN EFI_USB_PORT_STATUS *PortState ); /** @@ -866,11 +862,11 @@ XhcPeiPollPortStatusChange ( **/ EFI_STATUS XhcPeiConfigHubContext ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 PortNum, - IN UINT8 TTT, - IN UINT8 MTT + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 PortNum, + IN UINT8 TTT, + IN UINT8 MTT ); /** @@ -887,11 +883,11 @@ XhcPeiConfigHubContext ( **/ EFI_STATUS XhcPeiConfigHubContext64 ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 PortNum, - IN UINT8 TTT, - IN UINT8 MTT + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 PortNum, + IN UINT8 TTT, + IN UINT8 MTT ); /** @@ -907,10 +903,10 @@ XhcPeiConfigHubContext64 ( **/ EFI_STATUS XhcPeiSetConfigCmd ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 DeviceSpeed, - IN USB_CONFIG_DESCRIPTOR *ConfigDesc + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 DeviceSpeed, + IN USB_CONFIG_DESCRIPTOR *ConfigDesc ); /** @@ -926,10 +922,10 @@ XhcPeiSetConfigCmd ( **/ EFI_STATUS XhcPeiSetConfigCmd64 ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 DeviceSpeed, - IN USB_CONFIG_DESCRIPTOR *ConfigDesc + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 DeviceSpeed, + IN USB_CONFIG_DESCRIPTOR *ConfigDesc ); /** @@ -946,9 +942,9 @@ XhcPeiSetConfigCmd64 ( EFI_STATUS EFIAPI XhcPeiStopEndpoint ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 Dci + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 Dci ); /** @@ -965,9 +961,9 @@ XhcPeiStopEndpoint ( EFI_STATUS EFIAPI XhcPeiResetEndpoint ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 Dci + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 Dci ); /** @@ -986,10 +982,10 @@ XhcPeiResetEndpoint ( EFI_STATUS EFIAPI XhcPeiSetTrDequeuePointer ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT8 Dci, - IN URB *Urb + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT8 Dci, + IN URB *Urb ); /** @@ -1007,11 +1003,11 @@ XhcPeiSetTrDequeuePointer ( **/ EFI_STATUS XhcPeiInitializeDeviceSlot ( - IN PEI_XHC_DEV *Xhc, - IN USB_DEV_ROUTE ParentRouteChart, - IN UINT16 ParentPort, - IN USB_DEV_ROUTE RouteChart, - IN UINT8 DeviceSpeed + IN PEI_XHC_DEV *Xhc, + IN USB_DEV_ROUTE ParentRouteChart, + IN UINT16 ParentPort, + IN USB_DEV_ROUTE RouteChart, + IN UINT8 DeviceSpeed ); /** @@ -1029,11 +1025,11 @@ XhcPeiInitializeDeviceSlot ( **/ EFI_STATUS XhcPeiInitializeDeviceSlot64 ( - IN PEI_XHC_DEV *Xhc, - IN USB_DEV_ROUTE ParentRouteChart, - IN UINT16 ParentPort, - IN USB_DEV_ROUTE RouteChart, - IN UINT8 DeviceSpeed + IN PEI_XHC_DEV *Xhc, + IN USB_DEV_ROUTE ParentRouteChart, + IN UINT16 ParentPort, + IN USB_DEV_ROUTE RouteChart, + IN UINT8 DeviceSpeed ); /** @@ -1048,9 +1044,9 @@ XhcPeiInitializeDeviceSlot64 ( **/ EFI_STATUS XhcPeiEvaluateContext ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT32 MaxPacketSize + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT32 MaxPacketSize ); /** @@ -1065,9 +1061,9 @@ XhcPeiEvaluateContext ( **/ EFI_STATUS XhcPeiEvaluateContext64 ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId, - IN UINT32 MaxPacketSize + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId, + IN UINT32 MaxPacketSize ); /** @@ -1081,8 +1077,8 @@ XhcPeiEvaluateContext64 ( **/ EFI_STATUS XhcPeiDisableSlotCmd ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId ); /** @@ -1096,8 +1092,8 @@ XhcPeiDisableSlotCmd ( **/ EFI_STATUS XhcPeiDisableSlotCmd64 ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 SlotId + IN PEI_XHC_DEV *Xhc, + IN UINT8 SlotId ); /** @@ -1116,8 +1112,8 @@ XhcPeiDisableSlotCmd64 ( **/ EFI_STATUS XhcPeiRecoverHaltedEndpoint ( - IN PEI_XHC_DEV *Xhc, - IN URB *Urb + IN PEI_XHC_DEV *Xhc, + IN URB *Urb ); /** @@ -1135,8 +1131,8 @@ XhcPeiRecoverHaltedEndpoint ( **/ EFI_STATUS XhcPeiDequeueTrbFromEndpoint ( - IN PEI_XHC_DEV *Xhc, - IN URB *Urb + IN PEI_XHC_DEV *Xhc, + IN URB *Urb ); /** @@ -1157,19 +1153,19 @@ XhcPeiDequeueTrbFromEndpoint ( @return Created URB or NULL **/ -URB* +URB * XhcPeiCreateUrb ( - IN PEI_XHC_DEV *Xhc, - IN UINT8 DevAddr, - IN UINT8 EpAddr, - IN UINT8 DevSpeed, - IN UINTN MaxPacket, - IN UINTN Type, - IN EFI_USB_DEVICE_REQUEST *Request, - IN VOID *Data, - IN UINTN DataLen, - IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, - IN VOID *Context + IN PEI_XHC_DEV *Xhc, + IN UINT8 DevAddr, + IN UINT8 EpAddr, + IN UINT8 DevSpeed, + IN UINTN MaxPacket, + IN UINTN Type, + IN EFI_USB_DEVICE_REQUEST *Request, + IN VOID *Data, + IN UINTN DataLen, + IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback, + IN VOID *Context ); /** @@ -1181,8 +1177,8 @@ XhcPeiCreateUrb ( **/ VOID XhcPeiFreeUrb ( - IN PEI_XHC_DEV *Xhc, - IN URB *Urb + IN PEI_XHC_DEV *Xhc, + IN URB *Urb ); /** @@ -1196,8 +1192,8 @@ XhcPeiFreeUrb ( **/ EFI_STATUS XhcPeiCreateTransferTrb ( - IN PEI_XHC_DEV *Xhc, - IN URB *Urb + IN PEI_XHC_DEV *Xhc, + IN URB *Urb ); /** @@ -1225,9 +1221,9 @@ XhcPeiSyncTrsRing ( **/ VOID XhcPeiCreateTransferRing ( - IN PEI_XHC_DEV *Xhc, - IN UINTN TrbNum, - OUT TRANSFER_RING *TransferRing + IN PEI_XHC_DEV *Xhc, + IN UINTN TrbNum, + OUT TRANSFER_RING *TransferRing ); /** @@ -1243,9 +1239,9 @@ XhcPeiCreateTransferRing ( **/ EFI_STATUS XhcPeiCheckNewEvent ( - IN PEI_XHC_DEV *Xhc, - IN EVENT_RING *EvtRing, - OUT TRB_TEMPLATE **NewEvtTrb + IN PEI_XHC_DEV *Xhc, + IN EVENT_RING *EvtRing, + OUT TRB_TEMPLATE **NewEvtTrb ); /** @@ -1259,8 +1255,8 @@ XhcPeiCheckNewEvent ( **/ EFI_STATUS XhcPeiSyncEventRing ( - IN PEI_XHC_DEV *Xhc, - IN EVENT_RING *EvtRing + IN PEI_XHC_DEV *Xhc, + IN EVENT_RING *EvtRing ); /** @@ -1272,8 +1268,8 @@ XhcPeiSyncEventRing ( **/ VOID XhcPeiCreateEventRing ( - IN PEI_XHC_DEV *Xhc, - OUT EVENT_RING *EventRing + IN PEI_XHC_DEV *Xhc, + OUT EVENT_RING *EventRing ); /** @@ -1284,7 +1280,7 @@ XhcPeiCreateEventRing ( **/ VOID XhcPeiInitSched ( - IN PEI_XHC_DEV *Xhc + IN PEI_XHC_DEV *Xhc ); /** @@ -1295,7 +1291,7 @@ XhcPeiInitSched ( **/ VOID XhcPeiFreeSched ( - IN PEI_XHC_DEV *Xhc + IN PEI_XHC_DEV *Xhc ); #endif