X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdePkg%2FInclude%2FIndustryStandard%2FSdramSpd.h;h=68f90454a565136dde5fe1c45e34f766b5d375d8;hb=4994588211f03b41031b21fd8c6570191b5e53f7;hp=59302ee7dae1c5fbc2ff60e38018409c0517ca7f;hpb=568eb0cb4be2a61d7ae6273582438fd80223f49c;p=mirror_edk2.git
diff --git a/MdePkg/Include/IndustryStandard/SdramSpd.h b/MdePkg/Include/IndustryStandard/SdramSpd.h
index 59302ee7da..68f90454a5 100644
--- a/MdePkg/Include/IndustryStandard/SdramSpd.h
+++ b/MdePkg/Include/IndustryStandard/SdramSpd.h
@@ -1,18 +1,22 @@
-/**@file
+/** @file
This file contains definitions for the SPD fields on an SDRAM.
-
- Copyright (c) 2007, Intel Corporation
- All rights reserved. This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
-#ifndef _SDRAM_SPD_H
-#define _SDRAM_SPD_H
+#ifndef _SDRAM_SPD_H_
+#define _SDRAM_SPD_H_
+
+#include
+#include
+#include
//
// SDRAM SPD field definitions
@@ -32,12 +36,12 @@
#define SPD_SDRAM_CAS_LATENCY 18
#define SPD_SDRAM_MODULE_ATTR 21
-#define SPD_SDRAM_TCLK1_PULSE 9 // cycle time for highest cas latency
-#define SPD_SDRAM_TAC1_PULSE 10 // access time for highest cas latency
-#define SPD_SDRAM_TCLK2_PULSE 23 // cycle time for 2nd highest cas latency
-#define SPD_SDRAM_TAC2_PULSE 24 // access time for 2nd highest cas latency
-#define SPD_SDRAM_TCLK3_PULSE 25 // cycle time for 3rd highest cas latency
-#define SPD_SDRAM_TAC3_PULSE 26 // access time for 3rd highest cas latency
+#define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency
#define SPD_SDRAM_MIN_PRECHARGE 27
#define SPD_SDRAM_ACTIVE_MIN 28
#define SPD_SDRAM_RAS_CAS 29
@@ -47,15 +51,20 @@
//
// Memory Type Definitions
//
-#define SPD_VAL_SDR_TYPE 4 // SDR SDRAM memory
-#define SPD_VAL_DDR_TYPE 7 // DDR SDRAM memory
-#define SPD_VAL_DDR2_TYPE 8 // DDR2 SDRAM memory
+#define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory
+#define SPD_VAL_DDR3_TYPE 11 ///< DDR3 SDRAM memory
+#define SPD_VAL_DDR4_TYPE 12 ///< DDR4 SDRAM memory
+#define SPD_VAL_LPDDR3_TYPE 15 ///< LPDDR3 SDRAM memory
+#define SPD_VAL_LPDDR4_TYPE 16 ///< LPDDR4 SDRAM memory
+
//
// ECC Type Definitions
//
-#define SPD_ECC_TYPE_NONE 0x00 // No error checking
-#define SPD_ECC_TYPE_PARITY 0x01 // No error checking
-#define SPD_ECC_TYPE_ECC 0x02 // Error checking only
+#define SPD_ECC_TYPE_NONE 0x00 ///< No error checking
+#define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking
+#define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only
//
// Module Attributes (Bit positions)
//