X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdePkg%2FInclude%2FPpi%2FPciCfg2.h;h=451796f7f4d122ebf9337dfd63dcf1f220d317a2;hb=2f88bd3a1296c522317f1c21377876de63de5be7;hp=95702c60f0d5037d032bd0b9ab4c38d7e83c43b3;hpb=de1fad6887bf8f92b4a84bc14877ace68873ee8f;p=mirror_edk2.git

diff --git a/MdePkg/Include/Ppi/PciCfg2.h b/MdePkg/Include/Ppi/PciCfg2.h
index 95702c60f0..451796f7f4 100644
--- a/MdePkg/Include/Ppi/PciCfg2.h
+++ b/MdePkg/Include/Ppi/PciCfg2.h
@@ -1,17 +1,11 @@
 /** @file
   This file declares PciCfg2 PPI.
 
-  This ppi Provides platform or chipset-specific access to 
+  This ppi Provides platform or chipset-specific access to
   the PCI configuration space for a specific PCI segment.
 
-  Copyright (c) 2006 - 2009, Intel Corporation
-  All rights reserved. This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
 
   @par Revision Reference:
   This PPI is introduced in PI Version 1.0.
@@ -26,14 +20,14 @@
 #define EFI_PEI_PCI_CFG2_PPI_GUID \
   { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }
 
-typedef struct _EFI_PEI_PCI_CFG2_PPI   EFI_PEI_PCI_CFG2_PPI;
+typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;
 
-#define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \
+#define EFI_PEI_PCI_CFG_ADDRESS(bus, dev, func, reg) \
   (UINT64) ( \
   (((UINTN) bus) << 24) | \
   (((UINTN) dev) << 16) | \
   (((UINTN) func) << 8) | \
-  (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))));
+  (((UINTN) (reg)) < 256 ? ((UINTN) (reg)) : (UINT64) (LShiftU64 ((UINT64) (reg), 32))))
 
 ///
 /// EFI_PEI_PCI_CFG_PPI_WIDTH
@@ -42,7 +36,7 @@ typedef enum {
   ///
   ///  8-bit access
   ///
-  EfiPeiPciCfgWidthUint8  = 0,
+  EfiPeiPciCfgWidthUint8 = 0,
   ///
   /// 16-bit access
   ///
@@ -66,26 +60,26 @@ typedef struct {
   /// 8-bit register offset within the PCI configuration space for a given device's function
   /// space.
   ///
-  UINT8   Register;
+  UINT8     Register;
   ///
   /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a
   /// given device.
   ///
-  UINT8   Function;
+  UINT8     Function;
   ///
   /// Only the 5 least-significant bits are used to encode one of 32 possible devices.
   ///
-  UINT8   Device;
+  UINT8     Device;
   ///
   /// 8-bit value to encode between 0 and 255 buses.
   ///
-  UINT8   Bus;
+  UINT8     Bus;
   ///
   /// Register number in PCI configuration space. If this field is zero, then Register is used
   /// for the register number. If this field is non-zero, then Register is ignored and this field
   /// is used for the register number.
   ///
-  UINT32  ExtendedRegister;
+  UINT32    ExtendedRegister;
 } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;
 
 /**
@@ -120,11 +114,10 @@ EFI_STATUS
   IN        EFI_PEI_PCI_CFG_PPI_WIDTH Width,
   IN        UINT64                    Address,
   IN OUT    VOID                      *Buffer
-);
-
+  );
 
 /**
-  Performs a read-modify-write operation on the contents 
+  Performs a read-modify-write operation on the contents
   from a given location in the PCI configuration space.
 
   @param  PeiServices     An indirect pointer to the PEI Services Table
@@ -162,23 +155,22 @@ EFI_STATUS
   IN        UINT64                    Address,
   IN        VOID                      *SetBits,
   IN        VOID                      *ClearBits
-);
+  );
 
 ///
 /// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI
 /// controllers behind a PCI root bridge controller.
 ///
 struct _EFI_PEI_PCI_CFG2_PPI {
-  EFI_PEI_PCI_CFG2_PPI_IO  Read;
-  EFI_PEI_PCI_CFG2_PPI_IO  Write;
-  EFI_PEI_PCI_CFG2_PPI_RW  Modify;
+  EFI_PEI_PCI_CFG2_PPI_IO    Read;
+  EFI_PEI_PCI_CFG2_PPI_IO    Write;
+  EFI_PEI_PCI_CFG2_PPI_RW    Modify;
   ///
   /// The PCI bus segment which the specified functions will access.
   ///
-  UINT16                  Segment;
+  UINT16                     Segment;
 };
 
-
-extern EFI_GUID gEfiPciCfg2PpiGuid;
+extern EFI_GUID  gEfiPciCfg2PpiGuid;
 
 #endif