X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdePkg%2FInclude%2FProtocol%2FCpu.h;h=3d25ad08f8e78a9ddf96fd50360da8f51f49e4c6;hb=2f88bd3a1296c522317f1c21377876de63de5be7;hp=edb63fdd51ab90b8a4e0ff7eab87913ccd420934;hpb=9319d2c2066a3798d1e2b6d29486d933896cbdb0;p=mirror_edk2.git diff --git a/MdePkg/Include/Protocol/Cpu.h b/MdePkg/Include/Protocol/Cpu.h index edb63fdd51..3d25ad08f8 100644 --- a/MdePkg/Include/Protocol/Cpu.h +++ b/MdePkg/Include/Protocol/Cpu.h @@ -3,14 +3,8 @@ This code abstracts the DXE core from processor implementation details. - Copyright (c) 2006 - 2008, Intel Corporation - All rights reserved. This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ @@ -22,7 +16,7 @@ #define EFI_CPU_ARCH_PROTOCOL_GUID \ { 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } } -typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL; +typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL; /// /// The type of flush operation @@ -61,14 +55,14 @@ VOID ); /** - This function flushes the range of addresses from Start to Start+Length - from the processor's data cache. If Start is not aligned to a cache line - boundary, then the bytes before Start to the preceding cache line boundary - are also flushed. If Start+Length is not aligned to a cache line boundary, - then the bytes past Start+Length to the end of the next cache line boundary - are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be - supported. If the data cache is fully coherent with all DMA operations, then - this function can just return EFI_SUCCESS. If the processor does not support + This function flushes the range of addresses from Start to Start+Length + from the processor's data cache. If Start is not aligned to a cache line + boundary, then the bytes before Start to the preceding cache line boundary + are also flushed. If Start+Length is not aligned to a cache line boundary, + then the bytes past Start+Length to the end of the next cache line boundary + are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be + supported. If the data cache is fully coherent with all DMA operations, then + this function can just return EFI_SUCCESS. If the processor does not support flushing a range of the data cache, then the entire data cache can be flushed. @param This The EFI_CPU_ARCH_PROTOCOL instance. @@ -81,7 +75,7 @@ VOID @retval EFI_SUCCESS The address range from Start to Start+Length was flushed from the processor's data cache. - @retval EFI_UNSUPPORTEDT The processor does not support the cache flush type specified + @retval EFI_UNSUPPORTED The processor does not support the cache flush type specified by FlushType. @retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed from the processor's data cache. @@ -96,9 +90,8 @@ EFI_STATUS IN EFI_CPU_FLUSH_TYPE FlushType ); - /** - This function enables interrupt processing by the processor. + This function enables interrupt processing by the processor. @param This The EFI_CPU_ARCH_PROTOCOL instance. @@ -112,7 +105,6 @@ EFI_STATUS IN EFI_CPU_ARCH_PROTOCOL *This ); - /** This function disables interrupt processing by the processor. @@ -128,10 +120,9 @@ EFI_STATUS IN EFI_CPU_ARCH_PROTOCOL *This ); - /** - This function retrieves the processor's current interrupt state a returns it in - State. If interrupts are currently enabled, then TRUE is returned. If interrupts + This function retrieves the processor's current interrupt state a returns it in + State. If interrupts are currently enabled, then TRUE is returned. If interrupts are currently disabled, then FALSE is returned. @param This The EFI_CPU_ARCH_PROTOCOL instance. @@ -149,12 +140,11 @@ EFI_STATUS OUT BOOLEAN *State ); - /** This function generates an INIT on the processor. If this function succeeds, then the - processor will be reset, and control will not be returned to the caller. If InitType is - not supported by this processor, or the processor cannot programmatically generate an - INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error + processor will be reset, and control will not be returned to the caller. If InitType is + not supported by this processor, or the processor cannot programmatically generate an + INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned. @param This The EFI_CPU_ARCH_PROTOCOL instance. @@ -173,11 +163,10 @@ EFI_STATUS IN EFI_CPU_INIT_TYPE InitType ); - /** - This function registers and enables the handler specified by InterruptHandler for a processor - interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the - handler for the processor interrupt or exception type specified by InterruptType is uninstalled. + This function registers and enables the handler specified by InterruptHandler for a processor + interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the + handler for the processor interrupt or exception type specified by InterruptType is uninstalled. The installed handler is called once for each processor interrupt or exception. @param This The EFI_CPU_ARCH_PROTOCOL instance. @@ -203,7 +192,6 @@ EFI_STATUS IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler ); - /** This function reads the processor timer specified by TimerIndex and returns it in TimerValue. @@ -230,7 +218,6 @@ EFI_STATUS OUT UINT64 *TimerPeriod OPTIONAL ); - /** This function modifies the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes. @@ -244,6 +231,8 @@ EFI_STATUS @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by BaseAddress and Length cannot be modified. @retval EFI_INVALID_PARAMETER Length is zero. + Attributes specified an illegal combination of attributes that + cannot be set together. @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of the memory resource range. @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory @@ -261,7 +250,6 @@ EFI_STATUS IN UINT64 Attributes ); - /// /// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE /// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt @@ -269,30 +257,30 @@ EFI_STATUS /// determining the processor frequency. /// struct _EFI_CPU_ARCH_PROTOCOL { - EFI_CPU_FLUSH_DATA_CACHE FlushDataCache; - EFI_CPU_ENABLE_INTERRUPT EnableInterrupt; - EFI_CPU_DISABLE_INTERRUPT DisableInterrupt; - EFI_CPU_GET_INTERRUPT_STATE GetInterruptState; - EFI_CPU_INIT Init; - EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler; - EFI_CPU_GET_TIMER_VALUE GetTimerValue; - EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes; + EFI_CPU_FLUSH_DATA_CACHE FlushDataCache; + EFI_CPU_ENABLE_INTERRUPT EnableInterrupt; + EFI_CPU_DISABLE_INTERRUPT DisableInterrupt; + EFI_CPU_GET_INTERRUPT_STATE GetInterruptState; + EFI_CPU_INIT Init; + EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler; + EFI_CPU_GET_TIMER_VALUE GetTimerValue; + EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes; /// - /// The number of timers that are available in a processor. The value in this - /// field is a constant that must not be modified after the CPU Architectural + /// The number of timers that are available in a processor. The value in this + /// field is a constant that must not be modified after the CPU Architectural /// Protocol is installed. All consumers must treat this as a read-only field. /// - UINT32 NumberOfTimers; + UINT32 NumberOfTimers; /// - /// The size, in bytes, of the alignment required for DMA buffer allocations. - /// This is typically the size of the largest data cache line in the platform. - /// The value in this field is a constant that must not be modified after the - /// CPU Architectural Protocol is installed. All consumers must treat this as - /// a read-only field. + /// The size, in bytes, of the alignment required for DMA buffer allocations. + /// This is typically the size of the largest data cache line in the platform. + /// The value in this field is a constant that must not be modified after the + /// CPU Architectural Protocol is installed. All consumers must treat this as + /// a read-only field. /// - UINT32 DmaBufferAlignment; + UINT32 DmaBufferAlignment; }; -extern EFI_GUID gEfiCpuArchProtocolGuid; +extern EFI_GUID gEfiCpuArchProtocolGuid; #endif