X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=MdePkg%2FLibrary%2FUefiPciSegmentLibPciRootBridgeIo%2FPciSegmentLib.c;h=beb8b64adfd11146c80a970d099073907395ba68;hb=070a76b19386875d96f945262e832183d61f43da;hp=bb8779d9e0493536370cd5d0be6f5622e0ad0813;hpb=62991af27f84e5f20e55dee6e1f90eb77ec5325e;p=mirror_edk2.git diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c index bb8779d9e0..beb8b64adf 100644 --- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c +++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/PciSegmentLib.c @@ -271,21 +271,19 @@ PciSegmentRegisterForRuntimeAccess ( Reads an 8-bit PCI configuration register. Reads and returns the 8-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - - @return The value read from the PCI configuration register. + @return The 8-bit PCI configuration register specified by Address. **/ UINT8 EFIAPI PciSegmentRead8 ( - IN UINT64 Address + IN UINT64 Address ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); @@ -296,15 +294,13 @@ PciSegmentRead8 ( /** Writes an 8-bit PCI configuration register. - Writes the 8-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - - If any reserved bits in Address are set, then ASSERT(). + Writes the 8-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + + If Address > 0x0FFFFFFF, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param Data The value to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. @return The value written to the PCI configuration register. @@ -312,103 +308,94 @@ PciSegmentRead8 ( UINT8 EFIAPI PciSegmentWrite8 ( - IN UINT64 Address, - IN UINT8 Data + IN UINT64 Address, + IN UINT8 Value ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0); - return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data); + return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value); } /** - Performs a bitwise OR of an 8-bit PCI configuration register with - an 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 8-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value. + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT8 EFIAPI PciSegmentOr8 ( - IN UINT64 Address, - IN UINT8 OrData + IN UINT64 Address, + IN UINT8 OrData ) { return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData)); } /** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit - value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 8-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value. + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. If any reserved bits in Address are set, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT8 EFIAPI PciSegmentAnd8 ( - IN UINT64 Address, - IN UINT8 AndData + IN UINT64 Address, + IN UINT8 AndData ) { return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData)); } /** - Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit - value, followed a bitwise OR with another 8-bit value. - - Reads the 8-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 8-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, + followed a bitwise OR with another 8-bit value. + + Reads the 8-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 8-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT8 EFIAPI PciSegmentAndThenOr8 ( - IN UINT64 Address, - IN UINT8 AndData, - IN UINT8 OrData + IN UINT64 Address, + IN UINT8 AndData, + IN UINT8 OrData ) { return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData)); @@ -438,9 +425,9 @@ PciSegmentAndThenOr8 ( UINT8 EFIAPI PciSegmentBitFieldRead8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit ) { return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit); @@ -472,10 +459,10 @@ PciSegmentBitFieldRead8 ( UINT8 EFIAPI PciSegmentBitFieldWrite8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 Value + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 Value ) { return PciSegmentWrite8 ( @@ -513,10 +500,10 @@ PciSegmentBitFieldWrite8 ( UINT8 EFIAPI PciSegmentBitFieldOr8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 OrData ) { return PciSegmentWrite8 ( @@ -554,10 +541,10 @@ PciSegmentBitFieldOr8 ( UINT8 EFIAPI PciSegmentBitFieldAnd8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData ) { return PciSegmentWrite8 ( @@ -598,11 +585,11 @@ PciSegmentBitFieldAnd8 ( UINT8 EFIAPI PciSegmentBitFieldAndThenOr8 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT8 AndData, - IN UINT8 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT8 AndData, + IN UINT8 OrData ) { return PciSegmentWrite8 ( @@ -615,21 +602,20 @@ PciSegmentBitFieldAndThenOr8 ( Reads a 16-bit PCI configuration register. Reads and returns the 16-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - - @return The value read from the PCI configuration register. + @return The 16-bit PCI configuration register specified by Address. **/ UINT16 EFIAPI PciSegmentRead16 ( - IN UINT64 Address + IN UINT64 Address ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); @@ -640,29 +626,28 @@ PciSegmentRead16 ( /** Writes a 16-bit PCI configuration register. - Writes the 16-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - + Writes the 16-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param Data The value to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. - @return The value written to the PCI configuration register. + @return The parameter of Value. **/ UINT16 EFIAPI PciSegmentWrite16 ( - IN UINT64 Address, - IN UINT16 Data + IN UINT64 Address, + IN UINT16 Value ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1); - return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data); + return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value); } /** @@ -677,6 +662,7 @@ PciSegmentWrite16 ( are serialized. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). @param Address Address that encodes the PCI Segment, Bus, Device, Function and Register. @@ -688,71 +674,68 @@ PciSegmentWrite16 ( UINT16 EFIAPI PciSegmentOr16 ( - IN UINT64 Address, - IN UINT16 OrData + IN UINT64 Address, + IN UINT16 OrData ) { return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData)); } /** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit - value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value. + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT16 EFIAPI PciSegmentAnd16 ( - IN UINT64 Address, - IN UINT16 AndData + IN UINT64 Address, + IN UINT16 AndData ) { return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData)); } /** - Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit - value, followed a bitwise OR with another 16-bit value. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 16-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, + followed a bitwise OR with another 16-bit value. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT16 EFIAPI PciSegmentAndThenOr16 ( - IN UINT64 Address, - IN UINT16 AndData, - IN UINT16 OrData + IN UINT64 Address, + IN UINT16 AndData, + IN UINT16 OrData ) { return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData)); @@ -766,6 +749,7 @@ PciSegmentAndThenOr16 ( returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -782,9 +766,9 @@ PciSegmentAndThenOr16 ( UINT16 EFIAPI PciSegmentBitFieldRead16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit ) { return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit); @@ -799,6 +783,7 @@ PciSegmentBitFieldRead16 ( 16-bit register is returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -816,10 +801,10 @@ PciSegmentBitFieldRead16 ( UINT16 EFIAPI PciSegmentBitFieldWrite16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 Value + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 Value ) { return PciSegmentWrite16 ( @@ -829,17 +814,12 @@ PciSegmentBitFieldWrite16 ( } /** - Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and - writes the result back to the bit field in the 16-bit port. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 16-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. Extra left bits in OrData are stripped. + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). If StartBit is greater than 15, then ASSERT(). If EndBit is greater than 15, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -857,10 +837,10 @@ PciSegmentBitFieldWrite16 ( UINT16 EFIAPI PciSegmentBitFieldOr16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 OrData ) { return PciSegmentWrite16 ( @@ -870,38 +850,39 @@ PciSegmentBitFieldOr16 ( } /** - Reads a bit field in a 16-bit PCI configuration register, performs a bitwise - AND, and writes the result back to the bit field in the 16-bit register. - - Reads the 16-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 16-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, + and writes the result back to the bit field in the 16-bit port. + + Reads the 16-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 16-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + Extra left bits in OrData are stripped. + If any reserved bits in Address are set, then ASSERT(). - If StartBit is greater than 15, then ASSERT(). - If EndBit is greater than 15, then ASSERT(). + If Address is not aligned on a 16-bit boundary, then ASSERT(). + If StartBit is greater than 7, then ASSERT(). + If EndBit is greater than 7, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). - @param Address PCI configuration register to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. @param StartBit The ordinal of the least significant bit in the bit field. - Range 0..15. + The ordinal of the least significant bit in a byte is bit 0. @param EndBit The ordinal of the most significant bit in the bit field. - Range 0..15. - @param AndData The value to AND with the PCI configuration register. + The ordinal of the most significant bit in a byte is bit 7. + @param AndData The value to AND with the read value from the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT16 EFIAPI PciSegmentBitFieldAnd16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData ) { return PciSegmentWrite16 ( @@ -942,11 +923,11 @@ PciSegmentBitFieldAnd16 ( UINT16 EFIAPI PciSegmentBitFieldAndThenOr16 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT16 AndData, - IN UINT16 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT16 AndData, + IN UINT16 OrData ) { return PciSegmentWrite16 ( @@ -959,21 +940,20 @@ PciSegmentBitFieldAndThenOr16 ( Reads a 32-bit PCI configuration register. Reads and returns the 32-bit PCI configuration register specified by Address. - This function must guarantee that all PCI read and write operations are - serialized. - + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. - @return The value read from the PCI configuration register. + @return The 32-bit PCI configuration register specified by Address. **/ UINT32 EFIAPI PciSegmentRead32 ( - IN UINT64 Address + IN UINT64 Address ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); @@ -984,119 +964,113 @@ PciSegmentRead32 ( /** Writes a 32-bit PCI configuration register. - Writes the 32-bit PCI configuration register specified by Address with the - value specified by Value. Value is returned. This function must guarantee - that all PCI read and write operations are serialized. - + Writes the 32-bit PCI configuration register specified by Address with the value specified by Value. + Value is returned. This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param Data The value to write. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param Value The value to write. - @return The value written to the PCI configuration register. + @return The parameter of Value. **/ UINT32 EFIAPI PciSegmentWrite32 ( - IN UINT64 Address, - IN UINT32 Data + IN UINT64 Address, + IN UINT32 Value ) { ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3); - return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data); + return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value); } /** - Performs a bitwise OR of a 32-bit PCI configuration register with - a 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise OR between the read result and the value specified by - OrData, and writes the result to the 32-bit PCI configuration register - specified by Address. The value written to the PCI configuration register is - returned. This function must guarantee that all PCI read and write operations - are serialized. + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value. + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise OR between the read result and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param OrData The value to OR with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentOr32 ( - IN UINT64 Address, - IN UINT32 OrData + IN UINT64 Address, + IN UINT32 OrData ) { return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData); } /** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit - value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value. + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentAnd32 ( - IN UINT64 Address, - IN UINT32 AndData + IN UINT64 Address, + IN UINT32 AndData ) { return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData); } /** - Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit - value, followed a bitwise OR with another 32-bit value. - - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, - performs a bitwise OR between the result of the AND operation and - the value specified by OrData, and writes the result to the 32-bit PCI - configuration register specified by Address. The value written to the PCI - configuration register is returned. This function must guarantee that all PCI - read and write operations are serialized. - + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, + followed a bitwise OR with another 32-bit value. + + Reads the 32-bit PCI configuration register specified by Address, + performs a bitwise AND between the read result and the value specified by AndData, + performs a bitwise OR between the result of the AND operation and the value specified by OrData, + and writes the result to the 32-bit PCI configuration register specified by Address. + The value written to the PCI configuration register is returned. + This function must guarantee that all PCI read and write operations are serialized. + If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). - @param Address Address that encodes the PCI Segment, Bus, Device, Function and - Register. - @param AndData The value to AND with the PCI configuration register. - @param OrData The value to OR with the result of the AND operation. + @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param AndData The value to AND with the PCI configuration register. + @param OrData The value to OR with the PCI configuration register. - @return The value written back to the PCI configuration register. + @return The value written to the PCI configuration register. **/ UINT32 EFIAPI PciSegmentAndThenOr32 ( - IN UINT64 Address, - IN UINT32 AndData, - IN UINT32 OrData + IN UINT64 Address, + IN UINT32 AndData, + IN UINT32 OrData ) { return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData); @@ -1110,6 +1084,7 @@ PciSegmentAndThenOr32 ( returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -1126,9 +1101,9 @@ PciSegmentAndThenOr32 ( UINT32 EFIAPI PciSegmentBitFieldRead32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit ) { return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit); @@ -1143,6 +1118,7 @@ PciSegmentBitFieldRead32 ( 32-bit register is returned. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). @@ -1160,10 +1136,10 @@ PciSegmentBitFieldRead32 ( UINT32 EFIAPI PciSegmentBitFieldWrite32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 Value + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 Value ) { return PciSegmentWrite32 ( @@ -1201,10 +1177,10 @@ PciSegmentBitFieldWrite32 ( UINT32 EFIAPI PciSegmentBitFieldOr32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 OrData ) { return PciSegmentWrite32 ( @@ -1217,17 +1193,18 @@ PciSegmentBitFieldOr32 ( Reads a bit field in a 32-bit PCI configuration register, performs a bitwise AND, and writes the result back to the bit field in the 32-bit register. - Reads the 32-bit PCI configuration register specified by Address, performs a - bitwise AND between the read result and the value specified by AndData, and - writes the result to the 32-bit PCI configuration register specified by - Address. The value written to the PCI configuration register is returned. - This function must guarantee that all PCI read and write operations are - serialized. Extra left bits in AndData are stripped. - + + Reads the 32-bit PCI configuration register specified by Address, performs a bitwise + AND between the read result and the value specified by AndData, and writes the result + to the 32-bit PCI configuration register specified by Address. The value written to + the PCI configuration register is returned. This function must guarantee that all PCI + read and write operations are serialized. Extra left bits in AndData are stripped. If any reserved bits in Address are set, then ASSERT(). + If Address is not aligned on a 32-bit boundary, then ASSERT(). If StartBit is greater than 31, then ASSERT(). If EndBit is greater than 31, then ASSERT(). If EndBit is less than StartBit, then ASSERT(). + @param Address PCI configuration register to write. @param StartBit The ordinal of the least significant bit in the bit field. @@ -1242,10 +1219,10 @@ PciSegmentBitFieldOr32 ( UINT32 EFIAPI PciSegmentBitFieldAnd32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData ) { return PciSegmentWrite32 ( @@ -1286,11 +1263,11 @@ PciSegmentBitFieldAnd32 ( UINT32 EFIAPI PciSegmentBitFieldAndThenOr32 ( - IN UINT64 Address, - IN UINTN StartBit, - IN UINTN EndBit, - IN UINT32 AndData, - IN UINT32 OrData + IN UINT64 Address, + IN UINTN StartBit, + IN UINTN EndBit, + IN UINT32 AndData, + IN UINT32 OrData ) { return PciSegmentWrite32 ( @@ -1302,28 +1279,32 @@ PciSegmentBitFieldAndThenOr32 ( /** Reads a range of PCI configuration registers into a caller supplied buffer. - Reads the range of PCI configuration registers specified by StartAddress - and Size into the buffer specified by Buffer. - This function only allows the PCI configuration registers from a single PCI function to be read. - Size is returned. - - If any reserved bits in StartAddress are set, then ASSERT(). + Reads the range of PCI configuration registers specified by StartAddress and + Size into the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be read. Size is + returned. When possible 32-bit PCI configuration read cycles are used to read + from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit + and 16-bit PCI configuration read cycles may be used at the beginning and the + end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT(). - @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, + Function and Register. @param Size Size in bytes of the transfer. @param Buffer Pointer to a buffer receiving the data read. - @return The parameter of Size. + @return Size **/ UINTN EFIAPI PciSegmentReadBuffer ( - IN UINT64 StartAddress, - IN UINTN Size, - OUT VOID *Buffer + IN UINT64 StartAddress, + IN UINTN Size, + OUT VOID *Buffer ) { UINTN ReturnValue; @@ -1393,18 +1374,23 @@ PciSegmentReadBuffer ( } /** - Copies the data in a caller supplied buffer to a specified range of PCI configuration space. - - Writes the range of PCI configuration registers specified by StartAddress - and Size from the buffer specified by Buffer. - This function only allows the PCI configuration registers from a single PCI function to be written. - Size is returned. - - If any reserved bits in StartAddress are set, then ASSERT(). + Copies the data in a caller supplied buffer to a specified range of PCI + configuration space. + + Writes the range of PCI configuration registers specified by StartAddress and + Size from the buffer specified by Buffer. This function only allows the PCI + configuration registers from a single PCI function to be written. Size is + returned. When possible 32-bit PCI configuration write cycles are used to + write from StartAdress to StartAddress + Size. Due to alignment restrictions, + 8-bit and 16-bit PCI configuration write cycles may be used at the beginning + and the end of the range. + + If StartAddress > 0x0FFFFFFF, then ASSERT(). If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT(). If Size > 0 and Buffer is NULL, then ASSERT(). - @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, Function, and Register. + @param StartAddress Starting address that encodes the PCI Segment, Bus, Device, + Function and Register. @param Size Size in bytes of the transfer. @param Buffer Pointer to a buffer containing the data to write. @@ -1414,9 +1400,9 @@ PciSegmentReadBuffer ( UINTN EFIAPI PciSegmentWriteBuffer ( - IN UINT64 StartAddress, - IN UINTN Size, - IN VOID *Buffer + IN UINT64 StartAddress, + IN UINTN Size, + IN VOID *Buffer ) { UINTN ReturnValue;