X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=OvmfPkg%2FPlatformPei%2FPlatform.c;h=1940e01640fd177aa5646ed7b7ed07e96fd11c73;hb=53596a72cd96f84c7ca83254246f3520a49861b1;hp=0763f21fac862d7ab1a1e68a82bdfe72d46f6850;hpb=b621bb0a3ce81cabc31e28e055e3206068d5aa77;p=mirror_edk2.git diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 0763f21fac..1940e01640 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -30,14 +30,12 @@ #include #include #include +#include #include #include #include #include -#include -#include -#include -#include +#include #include "Platform.h" #include "Cmos.h" @@ -63,6 +61,11 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = { }; +EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION; + +BOOLEAN mS3Supported = FALSE; + + VOID AddIoMemoryBaseSizeHob ( EFI_PHYSICAL_ADDRESS MemoryBase, @@ -168,16 +171,10 @@ AddUntestedMemoryRangeHob ( } VOID -XenMemMapInitialization ( +MemMapInitialization ( VOID ) { - EFI_E820_ENTRY64 *E820Map; - UINT32 E820EntriesCount; - EFI_STATUS Status; - - DEBUG ((EFI_D_INFO, "Using memory map provided by Xen\n")); - // // Create Memory Type Information HOB // @@ -203,92 +200,40 @@ XenMemMapInitialization ( // AddIoMemoryRangeHob (0x0A0000, BASE_1MB); - // - // Parse RAM in E820 map - // - Status = XenGetE820Map(&E820Map, &E820EntriesCount); + if (!mXen) { + UINT32 TopOfLowRam; + TopOfLowRam = GetSystemMemorySizeBelow4gb (); - ASSERT_EFI_ERROR (Status); - - if (E820EntriesCount > 0) { - EFI_E820_ENTRY64 *Entry; - UINT32 Loop; - - for (Loop = 0; Loop < E820EntriesCount; Loop++) { - Entry = E820Map + Loop; - - // - // Only care about RAM - // - if (Entry->Type != EfiAcpiAddressRangeMemory) { - continue; - } - - if (Entry->BaseAddr >= BASE_4GB) { - AddUntestedMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length); - } else { - AddMemoryBaseSizeHob (Entry->BaseAddr, Entry->Length); - } - - MtrrSetMemoryAttribute (Entry->BaseAddr, Entry->Length, CacheWriteBack); - } + // + // address purpose size + // ------------ -------- ------------------------- + // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) + // 0xFC000000 gap 44 MB + // 0xFEC00000 IO-APIC 4 KB + // 0xFEC01000 gap 1020 KB + // 0xFED00000 HPET 1 KB + // 0xFED00400 gap 1023 KB + // 0xFEE00000 LAPIC 1 MB + // + AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ? + BASE_2GB : TopOfLowRam, 0xFC000000); + AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); } } -VOID -MemMapInitialization ( - EFI_PHYSICAL_ADDRESS TopOfMemory - ) -{ - // - // Create Memory Type Information HOB - // - BuildGuidDataHob ( - &gEfiMemoryTypeInformationGuid, - mDefaultMemoryTypeInformation, - sizeof(mDefaultMemoryTypeInformation) - ); - - // - // Add PCI IO Port space available for PCI resource allocations. - // - BuildResourceDescriptorHob ( - EFI_RESOURCE_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED, - 0xC000, - 0x4000 - ); - - // - // Video memory + Legacy BIOS region - // - AddIoMemoryRangeHob (0x0A0000, BASE_1MB); - - // - // address purpose size - // ------------ -------- ------------------------- - // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) - // 0xFC000000 gap 44 MB - // 0xFEC00000 IO-APIC 4 KB - // 0xFEC01000 gap 1020 KB - // 0xFED00000 HPET 1 KB - // 0xFED00400 gap 1023 KB - // 0xFEE00000 LAPIC 1 MB - // - AddIoMemoryRangeHob (TopOfMemory < BASE_2GB ? BASE_2GB : TopOfMemory, 0xFC000000); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); - AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); -} - - VOID MiscInitialization ( VOID ) { + UINT16 HostBridgeDevId; + UINTN PmCmd; + UINTN Pmba; + UINTN PmRegMisc; + // // Disable A20 Mask // @@ -299,45 +244,66 @@ MiscInitialization ( // BuildCpuHob (36, 16); + // + // Query Host Bridge DID to determine platform type and save to PCD + // + HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); + switch (HostBridgeDevId) { + case INTEL_82441_DEVICE_ID: + PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); + Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); + PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80); + break; + case INTEL_Q35_MCH_DEVICE_ID: + PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); + Pmba = POWER_MGMT_REGISTER_Q35 (0x40); + PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80); + break; + default: + DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", + __FUNCTION__, HostBridgeDevId)); + ASSERT (FALSE); + return; + } + PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId); + // // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for // example by Xen) and skip the setup here. This matches the logic in // AcpiTimerLibConstructor (). // - if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) { + if ((PciRead8 (PmRegMisc) & 0x01) == 0) { // // The PEI phase should be exited with fully accessibe PIIX4 IO space: // 1. set PMBA // - PciAndThenOr32 ( - PCI_LIB_ADDRESS (0, 1, 3, 0x40), - (UINT32) ~0xFFC0, - PcdGet16 (PcdAcpiPmBaseAddress) - ); + PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress)); // // 2. set PCICMD/IOSE // - PciOr8 ( - PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET), - EFI_PCI_COMMAND_IO_SPACE - ); + PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); // // 3. set PMREGMISC/PMIOSE // - PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01); + PciOr8 (PmRegMisc, 0x01); } } VOID BootModeInitialization ( + VOID ) { - EFI_STATUS Status; + EFI_STATUS Status; + + if (CmosRead8 (0xF) == 0xFE) { + mBootMode = BOOT_ON_S3_RESUME; + } - Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION); + Status = PeiServicesSetBootMode (mBootMode); ASSERT_EFI_ERROR (Status); Status = PeiServicesInstallPpi (mPpiBootMode); @@ -409,40 +375,34 @@ InitializePlatform ( IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_PHYSICAL_ADDRESS TopOfMemory; - UINT32 XenLeaf; - - TopOfMemory = 0; - DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n")); DebugDumpCmos (); - XenLeaf = XenDetect (); + XenDetect (); + + if (QemuFwCfgS3Enabled ()) { + DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n")); + mS3Supported = TRUE; + } BootModeInitialization (); PublishPeiMemory (); - if (mXen) { - PcdSetBool (PcdPciDisableBusEnumeration, TRUE); - } else { - TopOfMemory = MemDetect (); - } + InitializeRamRegions (); if (mXen) { DEBUG ((EFI_D_INFO, "Xen was detected\n")); - InitializeXen (XenLeaf); + InitializeXen (); } - ReserveEmuVariableNvStore (); + if (mBootMode != BOOT_ON_S3_RESUME) { + ReserveEmuVariableNvStore (); - PeiFvInitialization (); + PeiFvInitialization (); - if (mXen) { - XenMemMapInitialization (); - } else { - MemMapInitialization (TopOfMemory); + MemMapInitialization (); } MiscInitialization ();