X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=OvmfPkg%2FPlatformPei%2FPlatform.c;h=fc98fc35e0781a88385ad015b7fcf3cd9f539319;hb=79d274b8b6b113248661c18f31c4be03c7da32de;hp=1940e01640fd177aa5646ed7b7ed07e96fd11c73;hpb=d55004dac9c762fa01c5656f7a2e6132ed7bfe38;p=mirror_edk2.git diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 1940e01640..fc98fc35e0 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -32,9 +32,11 @@ #include #include #include +#include #include #include #include +#include #include #include "Platform.h" @@ -61,6 +63,8 @@ EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = { }; +UINT16 mHostBridgeDevId; + EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION; BOOLEAN mS3Supported = FALSE; @@ -212,13 +216,18 @@ MemMapInitialization ( // 0xFEC00000 IO-APIC 4 KB // 0xFEC01000 gap 1020 KB // 0xFED00000 HPET 1 KB - // 0xFED00400 gap 1023 KB + // 0xFED00400 gap 111 KB + // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB + // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ? BASE_2GB : TopOfLowRam, 0xFC000000); AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { + AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + } AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB); } } @@ -229,10 +238,10 @@ MiscInitialization ( VOID ) { - UINT16 HostBridgeDevId; UINTN PmCmd; UINTN Pmba; - UINTN PmRegMisc; + UINTN AcpiCtlReg; + UINT8 AcpiEnBit; // // Disable A20 Mask @@ -240,41 +249,44 @@ MiscInitialization ( IoOr8 (0x92, BIT1); // - // Build the CPU hob with 36-bit addressing and 16-bits of IO space. + // Build the CPU HOB with guest RAM size dependent address width and 16-bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during + // S3 resume as well, so we build it unconditionally.) // - BuildCpuHob (36, 16); + BuildCpuHob (mPhysMemAddressWidth, 16); // - // Query Host Bridge DID to determine platform type and save to PCD + // Determine platform type and save Host Bridge DID to PCD // - HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); - switch (HostBridgeDevId) { + switch (mHostBridgeDevId) { case INTEL_82441_DEVICE_ID: - PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); - Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40); - PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80); + PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); + Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); + AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC); + AcpiEnBit = PIIX4_PMREGMISC_PMIOSE; break; case INTEL_Q35_MCH_DEVICE_ID: - PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); - Pmba = POWER_MGMT_REGISTER_Q35 (0x40); - PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80); + PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); + Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); + AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); + AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN; break; default: DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", - __FUNCTION__, HostBridgeDevId)); + __FUNCTION__, mHostBridgeDevId)); ASSERT (FALSE); return; } - PcdSet16 (PcdOvmfHostBridgePciDevId, HostBridgeDevId); + PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId); // - // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for - // example by Xen) and skip the setup here. This matches the logic in - // AcpiTimerLibConstructor (). + // If the appropriate IOspace enable bit is set, assume the ACPI PMBA + // has been configured (e.g., by Xen) and skip the setup here. + // This matches the logic in AcpiTimerLibConstructor (). // - if ((PciRead8 (PmRegMisc) & 0x01) == 0) { + if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) { // - // The PEI phase should be exited with fully accessibe PIIX4 IO space: + // The PEI phase should be exited with fully accessibe ACPI PM IO space: // 1. set PMBA // PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress)); @@ -285,9 +297,19 @@ MiscInitialization ( PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); // - // 3. set PMREGMISC/PMIOSE + // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN) + // + PciOr8 (AcpiCtlReg, AcpiEnBit); + } + + if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { + // + // Set Root Complex Register Block BAR // - PciOr8 (PmRegMisc, 0x01); + PciWrite32 ( + POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), + ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN + ); } } @@ -359,6 +381,41 @@ DebugDumpCmos ( } +/** + Set the SMBIOS entry point version for the generic SmbiosDxe driver. +**/ +STATIC +VOID +SmbiosVersionInitialization ( + VOID + ) +{ + FIRMWARE_CONFIG_ITEM Anchor; + UINTN AnchorSize; + SMBIOS_TABLE_ENTRY_POINT QemuAnchor; + UINT16 SmbiosVersion; + + if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor, + &AnchorSize)) || + AnchorSize != sizeof QemuAnchor) { + return; + } + + QemuFwCfgSelectItem (Anchor); + QemuFwCfgReadBytes (AnchorSize, &QemuAnchor); + if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 || + CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) { + return; + } + + SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 | + QemuAnchor.MinorVersion); + DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__, + SmbiosVersion)); + PcdSet16 (PcdSmbiosVersion, SmbiosVersion); +} + + /** Perform Platform PEI initialization. @@ -387,6 +444,7 @@ InitializePlatform ( } BootModeInitialization (); + AddressWidthInitialization (); PublishPeiMemory (); @@ -397,12 +455,19 @@ InitializePlatform ( InitializeXen (); } + // + // Query Host Bridge DID + // + mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID); + if (mBootMode != BOOT_ON_S3_RESUME) { ReserveEmuVariableNvStore (); PeiFvInitialization (); MemMapInitialization (); + + SmbiosVersionInitialization (); } MiscInitialization ();