X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=OvmfPkg%2FPlatformPei%2FPlatform.c;h=fc98fc35e0781a88385ad015b7fcf3cd9f539319;hb=79d274b8b6b113248661c18f31c4be03c7da32de;hp=c48fe974be71bf059f251466109cfe3ea6c0497b;hpb=4b455f7bf0da7ab11a6366a1ab9ac3c8905411a4;p=mirror_edk2.git

diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c
index c48fe974be..fc98fc35e0 100644
--- a/OvmfPkg/PlatformPei/Platform.c
+++ b/OvmfPkg/PlatformPei/Platform.c
@@ -30,10 +30,14 @@
 #include <Library/PciLib.h>
 #include <Library/PeimEntryPoint.h>
 #include <Library/PeiServicesLib.h>
+#include <Library/QemuFwCfgLib.h>
 #include <Library/ResourcePublicationLib.h>
+#include <Library/BaseMemoryLib.h>
 #include <Guid/MemoryTypeInformation.h>
 #include <Ppi/MasterBootMode.h>
 #include <IndustryStandard/Pci22.h>
+#include <IndustryStandard/SmBios.h>
+#include <OvmfPlatforms.h>
 
 #include "Platform.h"
 #include "Cmos.h"
@@ -59,6 +63,13 @@ EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {
 };
 
 
+UINT16 mHostBridgeDevId;
+
+EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+BOOLEAN mS3Supported = FALSE;
+
+
 VOID
 AddIoMemoryBaseSizeHob (
   EFI_PHYSICAL_ADDRESS        MemoryBase,
@@ -205,16 +216,19 @@ MemMapInitialization (
     // 0xFEC00000    IO-APIC                        4 KB
     // 0xFEC01000    gap                         1020 KB
     // 0xFED00000    HPET                           1 KB
-    // 0xFED00400    gap                         1023 KB
+    // 0xFED00400    gap                          111 KB
+    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB
+    // 0xFED20000    gap                          896 KB
     // 0xFEE00000    LAPIC                          1 MB
     //
     AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?
                          BASE_2GB : TopOfLowRam, 0xFC000000);
     AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);
     AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);
+    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
+      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);
+    }
     AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);
-  } else {
-    XenPublishRamRegions ();
   }
 }
 
@@ -224,55 +238,94 @@ MiscInitialization (
   VOID
   )
 {
+  UINTN  PmCmd;
+  UINTN  Pmba;
+  UINTN  AcpiCtlReg;
+  UINT8  AcpiEnBit;
+
   //
   // Disable A20 Mask
   //
   IoOr8 (0x92, BIT1);
 
   //
-  // Build the CPU hob with 36-bit addressing and 16-bits of IO space.
+  // Build the CPU HOB with guest RAM size dependent address width and 16-bits
+  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
+  // S3 resume as well, so we build it unconditionally.)
   //
-  BuildCpuHob (36, 16);
+  BuildCpuHob (mPhysMemAddressWidth, 16);
 
   //
-  // If PMREGMISC/PMIOSE is set, assume the ACPI PMBA has been configured (for
-  // example by Xen) and skip the setup here. This matches the logic in
-  // AcpiTimerLibConstructor ().
+  // Determine platform type and save Host Bridge DID to PCD
   //
-  if ((PciRead8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80)) & 0x01) == 0) {
+  switch (mHostBridgeDevId) {
+    case INTEL_82441_DEVICE_ID:
+      PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);
+      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
+      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
+      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;
+      break;
+    case INTEL_Q35_MCH_DEVICE_ID:
+      PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);
+      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
+      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
+      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;
+      break;
+    default:
+      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
+        __FUNCTION__, mHostBridgeDevId));
+      ASSERT (FALSE);
+      return;
+  }
+  PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);
+
+  //
+  // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
+  // has been configured (e.g., by Xen) and skip the setup here.
+  // This matches the logic in AcpiTimerLibConstructor ().
+  //
+  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
     //
-    // The PEI phase should be exited with fully accessibe PIIX4 IO space:
+    // The PEI phase should be exited with fully accessibe ACPI PM IO space:
     // 1. set PMBA
     //
-    PciAndThenOr32 (
-      PCI_LIB_ADDRESS (0, 1, 3, 0x40),
-      (UINT32) ~0xFFC0,
-      PcdGet16 (PcdAcpiPmBaseAddress)
-      );
+    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
 
     //
     // 2. set PCICMD/IOSE
     //
-    PciOr8 (
-      PCI_LIB_ADDRESS (0, 1, 3, PCI_COMMAND_OFFSET),
-      EFI_PCI_COMMAND_IO_SPACE
-      );
+    PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);
+
+    //
+    // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
+    //
+    PciOr8 (AcpiCtlReg, AcpiEnBit);
+  }
 
+  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
     //
-    // 3. set PMREGMISC/PMIOSE
+    // Set Root Complex Register Block BAR
     //
-    PciOr8 (PCI_LIB_ADDRESS (0, 1, 3, 0x80), 0x01);
+    PciWrite32 (
+      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),
+      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN
+      );
   }
 }
 
 
 VOID
 BootModeInitialization (
+  VOID
   )
 {
-  EFI_STATUS Status;
+  EFI_STATUS    Status;
 
-  Status = PeiServicesSetBootMode (BOOT_WITH_FULL_CONFIGURATION);
+  if (CmosRead8 (0xF) == 0xFE) {
+    mBootMode = BOOT_ON_S3_RESUME;
+  }
+
+  Status = PeiServicesSetBootMode (mBootMode);
   ASSERT_EFI_ERROR (Status);
 
   Status = PeiServicesInstallPpi (mPpiBootMode);
@@ -328,6 +381,41 @@ DebugDumpCmos (
 }
 
 
+/**
+  Set the SMBIOS entry point version for the generic SmbiosDxe driver.
+**/
+STATIC
+VOID
+SmbiosVersionInitialization (
+  VOID
+  )
+{
+  FIRMWARE_CONFIG_ITEM     Anchor;
+  UINTN                    AnchorSize;
+  SMBIOS_TABLE_ENTRY_POINT QemuAnchor;
+  UINT16                   SmbiosVersion;
+
+  if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,
+                      &AnchorSize)) ||
+      AnchorSize != sizeof QemuAnchor) {
+    return;
+  }
+
+  QemuFwCfgSelectItem (Anchor);
+  QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);
+  if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||
+      CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {
+    return;
+  }
+
+  SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |
+                           QemuAnchor.MinorVersion);
+  DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,
+    SmbiosVersion));
+  PcdSet16 (PcdSmbiosVersion, SmbiosVersion);
+}
+
+
 /**
   Perform Platform PEI initialization.
 
@@ -350,24 +438,37 @@ InitializePlatform (
 
   XenDetect ();
 
+  if (QemuFwCfgS3Enabled ()) {
+    DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));
+    mS3Supported = TRUE;
+  }
+
   BootModeInitialization ();
+  AddressWidthInitialization ();
 
   PublishPeiMemory ();
 
-  if (!mXen) {
-    MemDetect ();
-  }
+  InitializeRamRegions ();
 
   if (mXen) {
     DEBUG ((EFI_D_INFO, "Xen was detected\n"));
     InitializeXen ();
   }
 
-  ReserveEmuVariableNvStore ();
+  //
+  // Query Host Bridge DID
+  //
+  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
+
+  if (mBootMode != BOOT_ON_S3_RESUME) {
+    ReserveEmuVariableNvStore ();
 
-  PeiFvInitialization ();
+    PeiFvInitialization ();
 
-  MemMapInitialization ();
+    MemMapInitialization ();
+
+    SmbiosVersionInitialization ();
+  }
 
   MiscInitialization ();