X-Git-Url: https://git.proxmox.com/?a=blobdiff_plain;f=OvmfPkg%2FPlatformPei%2FPlatform.h;h=f942e61bb4f90ab16bbc18420ca97f582e1b5fea;hb=7ef0dae092afcfb6fab7e8372c78097672168c4a;hp=7344c610bb2d3935d17067fac64e677804e9f0e5;hpb=36658fff454167c716993cf649f6172361b0e7b2;p=mirror_edk2.git diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 7344c610bb..f942e61bb4 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -1,7 +1,7 @@ /** @file Platform PEI module include file. - Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -15,6 +15,8 @@ #ifndef _PLATFORM_PEI_H_INCLUDED_ #define _PLATFORM_PEI_H_INCLUDED_ +#include + VOID AddIoMemoryBaseSizeHob ( EFI_PHYSICAL_ADDRESS MemoryBase, @@ -40,21 +42,20 @@ AddMemoryRangeHob ( ); VOID -AddUntestedMemoryBaseSizeHob ( +AddReservedMemoryBaseSizeHob ( EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize + UINT64 MemorySize, + BOOLEAN Cacheable ); VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize +AddressWidthInitialization ( + VOID ); VOID -AddUntestedMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit +Q35TsegMbytesInitialization ( + VOID ); EFI_STATUS @@ -62,8 +63,13 @@ PublishPeiMemory ( VOID ); -EFI_PHYSICAL_ADDRESS -MemDetect ( +UINT32 +GetSystemMemorySizeBelow4gb ( + VOID + ); + +VOID +InitializeRamRegions ( VOID ); @@ -72,14 +78,41 @@ PeiFvInitialization ( VOID ); +VOID +InstallFeatureControlCallback ( + VOID + ); + EFI_STATUS InitializeXen ( - UINT32 XenLeaf + VOID ); -UINT32 +BOOLEAN XenDetect ( VOID ); +VOID +AmdSevInitialize ( + VOID + ); + +extern BOOLEAN mXen; + +VOID +XenPublishRamRegions ( + VOID + ); + +extern EFI_BOOT_MODE mBootMode; + +extern BOOLEAN mS3Supported; + +extern UINT8 mPhysMemAddressWidth; + +extern UINT32 mMaxCpuCount; + +extern UINT16 mHostBridgeDevId; + #endif // _PLATFORM_PEI_H_INCLUDED_